Christoforos Kozyrakis
Associate Professor of Electrical Engineering and of Computer Science
Bio
Christos Kozyrakis research focuses on making computer system of any size faster, cheaper, and greener. His current work focuses on the hardware architecture, runtime environment, programming models, and security infrastructure for warehouse-scale data centers and many-core chips with thousands of general purpose cores and fixed functions accelerators.
Academic Appointments
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Associate Professor, Electrical Engineering
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Associate Professor, Computer Science
Honors & Awards
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Research Grant, Okawa Foundation (2005)
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Career Award, National Science Foundation (2006)
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Faculty Award, IBM (2006)
Boards, Advisory Committees, Professional Organizations
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Willard R. and Inez Kerr Bell faculty scholar, Stanford University (2009 - 2011)
Professional Education
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PhD, University of California at Berkeley, Computer Science (2002)
2014-15 Courses
- Advanced Multi-Core Systems
CS 316, EE 382E (Aut) - Computer Systems Architecture
EE 282 (Spr) - Digital Systems Architecture
EE 180 (Win) -
Independent Studies (23)
- Advanced Reading and Research
CS 499 (Aut, Win, Spr, Sum) - Advanced Reading and Research
CS 499P (Aut, Win, Spr, Sum) - Computer Laboratory
CS 393 (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390A (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390B (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390C (Aut, Win, Spr, Sum) - Independent Database Project
CS 395 (Aut, Win, Spr, Sum) - Independent Project
CS 399 (Aut, Win, Spr, Sum) - Independent Project
CS 399P (Aut, Win, Spr, Sum) - Independent Work
CS 199 (Aut, Win, Spr, Sum) - Independent Work
CS 199P (Aut, Win, Spr, Sum) - Master's Thesis and Thesis Research
EE 300 (Aut, Win, Spr, Sum) - Part-Time Curricular Practical Training
CS 390Q (Spr) - Part-Time Curricular Practical Training
CS 390R (Sum) - Part-time Curricular Practical Training
CS 390P (Win, Spr) - Programming Service Project
CS 192 (Aut, Win, Spr, Sum) - Senior Project
CS 191 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering
EE 191 (Aut, Win, Spr) - Special Studies and Reports in Electrical Engineering
EE 391 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering (WIM)
EE 191W (Aut, Win, Spr) - Special Studies or Projects in Electrical Engineering
EE 190 (Aut, Win, Spr) - Special Studies or Projects in Electrical Engineering
EE 390 (Aut, Win, Spr, Sum) - Writing Intensive Senior Project (WIM)
CS 191W (Aut, Win, Spr)
- Advanced Reading and Research
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Prior Year Courses
2013-14 Courses
- Advanced Multi-Core Systems
CS 316, EE 382E (Aut) - Computer Systems Architecture
EE 282 (Spr) - Digital Systems II
EE 108B (Win)
2012-13 Courses
- Advanced Multi-Core Systems
CS 316, EE 382E (Aut) - Computer Systems Architecture
EE 282 (Spr) - Digital Systems II
EE 108B (Win)
2011-12 Courses
- Computer Systems Architecture
EE 282 (Spr) - Digital Systems II
EE 108B (Win) - Digital Systems II
OSPKYOTO 33 (Spr)
- Advanced Multi-Core Systems
Journal Articles
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QUALITY-OF-SERVICE-AWARE SCHEDULING IN HETEROGENEOUS DATACENTERS WITH PARAGON
IEEE MICRO
2014; 34 (3): 17-30
View details for Web of Science ID 000337895100004
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QoS-Aware Scheduling in Heterogeneous Datacenters with Paragon
ACM TRANSACTIONS ON COMPUTER SYSTEMS
2013; 31 (4)
View details for DOI 10.1145/2556583
View details for Web of Science ID 000329130800004
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Paragon: QoS-Aware Scheduling for Heterogeneous Datacenters
ACM SIGPLAN NOTICES
2013; 48 (4): 77-88
View details for Web of Science ID 000321213100007
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Guest Editors' Introduction SELECTED RESEARCH FROM HOT CHIPS 24
IEEE MICRO
2013; 33 (2): 6-7
View details for Web of Science ID 000316977900002
- Measuring and analyzing the energy use of enterprise computing systems Sustainable Computing: Informatics and Systems 2013
- QoS-Aware Scheduling in Heterogeneous Datacenters with Paragon ACM Transactions on Computer Systems (TOCS) 2013; 31 (4)
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The Netflix Challenge: Datacenter Edition
IEEE COMPUTER ARCHITECTURE LETTERS
2013; 12 (1): 29-32
View details for DOI 10.1109/L-CA.2012.10
View details for Web of Science ID 000320993000009
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Decoupling Datacenter Storage Studies from Access to Large-Scale Applications
IEEE COMPUTER ARCHITECTURE LETTERS
2012; 11 (2): 53-56
View details for DOI 10.1109/L-CA.2011.37
View details for Web of Science ID 000312559500007
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SCALABLE AND EFFICIENT FINE-GRAINED CACHE PARTITIONING WITH VANTAGE
IEEE MICRO
2012; 32 (3): 26-37
View details for Web of Science ID 000304792200005
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Hardware Acceleration of Transactional Memory on Commodity Systems
ACM SIGPLAN NOTICES
2012; 47 (4): 27-38
View details for DOI 10.1145/2248487.1950372
View details for Web of Science ID 000307565500004
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Improving System Energy Efficiency with Memory Rank Subsetting
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2012; 9 (1)
View details for DOI 10.1145/2133382.2133386
View details for Web of Science ID 000302249400004
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Towards Energy-Proportional Datacenter Memory with Mobile DRAM
2012 39TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA)
2012: 37-48
View details for Web of Science ID 000309010000004
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A Case of System-level Hardware/Software Co-design and Co-verification of a Commodity Multi-Processor System with Custom Hardware
CODES+ISSS'12:PROCEEDINGS OF THE TENTH ACM INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE-CODESIGN AND SYSTEM SYNTHESIS
2012: 513-519
View details for Web of Science ID 000320320800059
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SCD: A Scalable Coherence Directory with Flexible Sharer Set Encoding
2012 IEEE 18TH INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA)
2012: 129-140
View details for Web of Science ID 000308957200011
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Green Enterprise Computing Data: Assumptions and Realities
2012 INTERNATIONAL GREEN COMPUTING CONFERENCE (IGCC)
2012
View details for Web of Science ID 000309942300020
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Understanding Sources of Inefficiency in General-Purpose Chips
COMMUNICATIONS OF THE ACM
2011; 54 (10): 85-93
View details for DOI 10.1145/2001269.2001291
View details for Web of Science ID 000296022500021
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The Case for RAMCloud
COMMUNICATIONS OF THE ACM
2011; 54 (7): 121-130
View details for DOI 10.1145/1965724.1965751
View details for Web of Science ID 000293277800033
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Decoupling Datacenter Studies from Access to Large-Scale Applications: A Modeling Approach for Storage Workloads
2011 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION (IISWC)
2011: 51-60
View details for Web of Science ID 000299350700005
- Understanding Sources of Inefficiency in General-Purpose Chips Communications of the ACM (CACM) 2011; 54 (10)
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Vantage: Scalable and Efficient Fine-Grain Cache Partitioning
ISCA 2011: PROCEEDINGS OF THE 38TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
2011: 57-68
View details for Web of Science ID 000292709800006
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Hardware Acceleration of Transactional Memory on Commodity Systems
ASPLOS XVI: SIXTEENTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS
2011: 27-38
View details for Web of Science ID 000290968100004
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SERVER ENGINEERING INSIGHTS FOR LARGE-SCALE ONLINE SERVICES
IEEE MICRO
2010; 30 (4): 8-19
View details for Web of Science ID 000280949100003
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An Analysis of On-Chip Interconnection Networks for Large-Scale Chip Multiprocessors
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2010; 7 (1)
View details for DOI 10.1145/1756065.1736069
View details for Web of Science ID 000277924800004
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Flexible Architectural Support for Fine-Grain Scheduling
ACM SIGPLAN NOTICES
2010; 45 (3): 311-322
View details for Web of Science ID 000275926700026
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Understanding Sources of Inefficiency in General-Purpose Chips
ISCA 2010: THE 37TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
2010: 37-47
View details for Web of Science ID 000287049300005
- Tainting is Not Pointless ACM SIGOPS Operating Systems Review 2010; 44 (2)
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Implementing and Evaluating Nested Parallel Transactions in Software Transactional Memory
SPAA '10: PROCEEDINGS OF THE TWENTY-SECOND ANNUAL SYMPOSIUM ON PARALLELISM IN ALGORITHMS AND ARCHITECTURES
2010: 253-262
View details for Web of Science ID 000281485500036
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Power Management of Datacenter Workloads Using Per-Core Power Gating
IEEE COMPUTER ARCHITECTURE LETTERS
2009; 8 (2): 48-51
View details for DOI 10.1109/L-CA.2009.46
View details for Web of Science ID 000207924800005
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HOT CHIPS TURNS 20
IEEE MICRO
2009; 29 (2): 4-5
View details for Web of Science ID 000264804100002
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A Memory System Design Framework: Creating Smart Memories
ISCA 2009: 36TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
2009: 406-417
View details for Web of Science ID 000268225000037
- The case for RAMClouds: scalable high-performance storage entirely in DRAM ACM SIGOPS Operating Systems Review 2009; 43 (4)
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Future Scaling of Processor-Memory Interfaces
PROCEEDINGS OF THE CONFERENCE ON HIGH PERFORMANCE COMPUTING NETWORKING, STORAGE AND ANALYSIS
2009
View details for Web of Science ID 000320136800015
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Fast Memory Snapshot for Concurrent Programming without Synchronization
ICS'09: PROCEEDINGS OF THE 2009 ACM SIGARCH INTERNATIONAL CONFERENCE ON SUPERCOMPUTING
2009: 117-125
View details for Web of Science ID 000268247500012
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Decoupling Dynamic Information Flow Tracking with a Dedicated Coprocessor
2009 IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS & NETWORKS (DSN 2009)
2009: 105-114
View details for Web of Science ID 000275174400012
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Feedback-Directed Barrier Optimization in a Strongly Isolated STM
ACM SIGPLAN NOTICES
2009; 44 (1): 213-225
View details for Web of Science ID 000272013800020
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Phoenix Rebirth: Scalable MapReduce on a Large-Scale Shared-Memory System
PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION
2009: 198-207
View details for Web of Science ID 000274997900021
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Comparative Evaluation of Memory Models for Chip Multiprocessors
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
2008; 5 (3)
View details for DOI 10.1145/1455650.1455651
View details for Web of Science ID 000261844300001
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Transactional memory
COMMUNICATIONS OF THE ACM
2008; 51 (7): 80-88
View details for DOI 10.1145/1364782.1364800
View details for Web of Science ID 000257116300019
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Improving Software Concurrency with Hardware-assisted Memory Snapshot
SPAA'08: PROCEEDINGS OF THE TWENTIETH ANNUAL SYMPOSIUM ON PARALLELISM IN ALGORITHMS AND ARCHITECTURES
2008: 363-363
View details for Web of Science ID 000266217200050
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ASeD: Availability, Security, and Debugging Support using Transactional Memory
SPAA'08: PROCEEDINGS OF THE TWENTIETH ANNUAL SYMPOSIUM ON PARALLELISM IN ALGORITHMS AND ARCHITECTURES
2008: 366-366
View details for Web of Science ID 000266217200053
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STAMP: Stanford Transactional Applications for Multi-Processing
2008 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION
2008: 31-42
View details for Web of Science ID 000263063500004
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Thread-Safe Dynamic Binary Translation using Transactional Memory
2008 IEEE 14TH INTERNATIONAL SYMPOSIUM ON HIGH PEFORMANCE COMPUTER ARCHITECTURE
2008: 256-266
View details for Web of Science ID 000263593200024
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Models and metrics to enable energy-efficiency optimizations
COMPUTER
2007; 40 (12): 39-?
View details for Web of Science ID 000251428300011
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RAMP: Research accelerator for multiple processors
IEEE MICRO
2007; 27 (2): 46-57
View details for Web of Science ID 000247913200007
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Towards Soft Optimization Techniques for Parallel Cognitive Applications
SPAA'07: PROCEEDINGS OF THE NINETEENTH ANNUAL SYMPOSIUM ON PARALLELISM IN ALGORITHMS AND ARCHITECTURES
2007: 59-60
View details for Web of Science ID 000266371200009
- RAMP: Research Accelerator for Multiple Processors IEEE Micro 2007; 27 (2)
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Raksha: A Flexible Information Flow Architecture for Software Security
ISCA'07: 34TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, CONFERENCE PROCEEDINGS
2007: 482-493
View details for Web of Science ID 000265786200043
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A Practical FPGA-based Framework for Novel CMP Research
FPGA 2007: FIFTEENTH ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS
2007: 116-125
View details for Web of Science ID 000268330100013
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Transactional Collection Classes
PROCEEDINGS OF THE 2007 ACM SIGPLAN SYMPOSIUM ON PRINCIPLES AND PRACTICE OF PARALLEL PROGRAMMING PPOPP'07
2007: 56-67
View details for Web of Science ID 000266870900006
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ATLAS: A chip-multiprocessor with Transactional Memory support
2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3
2007: 3-8
View details for Web of Science ID 000252175700001
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Transactional memory: The hardware-software interface
IEEE MICRO
2007; 27 (1): 67-76
View details for Web of Science ID 000246455000009
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An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees
ISCA'07: 34TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, CONFERENCE PROCEEDINGS
2007: 69-80
View details for Web of Science ID 000265786200007
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Evaluating MapReduce for multi-core and multiprocessor systems
THIRTEENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS
2007: 13-24
View details for Web of Science ID 000245463100002
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Comparing Memory Systems for Chip Multiprocessors
ISCA'07: 34TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, CONFERENCE PROCEEDINGS
2007: 358-368
View details for Web of Science ID 000265786200032
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A scalable, non-blocking approach to transactional memory
THIRTEENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS
2007: 97-108
View details for Web of Science ID 000245463100010
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Register pointer architecture for efficient embedded processors
2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3
2007: 600-605
View details for Web of Science ID 000252175700101
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Tradeoffs in transactional memory virtualization
ACM SIGPLAN NOTICES
2006; 41 (11): 371-381
View details for Web of Science ID 000202972600035
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The ATOMO Sigma transactional programming language
ACM SIGPLAN NOTICES
2006; 41 (6): 1-13
View details for Web of Science ID 000202972100001
- Block Aware Instruction Set Architecture ACM Transactions on Architecture and Code Optimization 2006; 3 (3): 327-357
- Unlocking Concurrency: Multicore Programming with Transactional Memor ACM Queue 2006; 4 (10)
- Library-based Prefetching for Pointer Intensive Applications Online Technical Manuscript 2006
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The common case transactional behavior of multithreaded programs
TWELFTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS
2006: 271-282
View details for Web of Science ID 000237200400026
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Simultaneously improving code size, performance, and energy in embedded processors
2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS
2006: 222-227
View details for Web of Science ID 000243721600045
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Architectural semantics for practical Transactional Memory
33RD INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHTIECTURE, PROCEEDINGS
2006: 53-64
View details for Web of Science ID 000238976500005
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Vector lane threading
2006 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING, PROCEEDINGS
2006: 55-62
View details for Web of Science ID 000241495500006
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Heuristics for profile-driven method-level speculative parallelization
2005 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSSING, PROCEEDINGS
2005: 147-156
View details for Web of Science ID 000230567500016
- RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform UC Berkeley Technical Report UCB/CSD-05-1412 2005
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Autonomic power management schemes for Internet servers and data centers
GLOBECOM '05: IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, VOLS 1-6
2005: 943-947
View details for Web of Science ID 000234989601059
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Improving instruction delivery with a block-aware ISA
EURO-PAR 2005 PARALLEL PROCESSING, PROCEEDINGS
2005; 3648: 530-539
View details for Web of Science ID 000232259500060
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Energy-efficient and high-performance instruction fetch using a block-aware ISA
ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN
2005: 36-41
View details for Web of Science ID 000232431400007
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Characterization of TCC on chip-multiprocessors
PACT 2005: 14TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES
2005: 63-74
View details for Web of Science ID 000233637100006
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Transactional coherence and consistency: Simplifying parallel hardware and software
IEEE MICRO
2004; 24 (6): 92-103
View details for Web of Science ID 000226365900013
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The stream virtual machine
13TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION TECHNIQUES, PROCEEDINGS
2004: 267-277
View details for Web of Science ID 000224469900025
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Transactional memory coherence and consistency
31ST ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS
2004: 102-113
View details for Web of Science ID 000222915900009
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Scalable vector processors for embedded systems
IEEE MICRO
2003; 23 (6): 36-45
View details for Web of Science ID 000188257700007
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Overcoming the limitations of conventional vector processors
30TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS
2003: 399-409
View details for Web of Science ID 000183763700034
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Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
35TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-35), PROCEEDINGS
2002: 283-293
View details for Web of Science ID 000179945200024
- Vector IRAM: A Media-oriented Vector Processor with Embedded DRAM Technical Record of the 12th Hot Chips Conference 2000
- A Media-Enhanced Vector Architecture for Embedded Memory Systems Technical Report UCB-CSD-99-1059, University of California at Berkeley 1999
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A new direction for computer architecture research
COMPUTER
1998; 31 (11): 24-?
View details for Web of Science ID 000076716300016
- Scalable Processors for the Billion Transistors Era: IRAM IEEE Computer 1997; 30 (9): 75-58
- A Case for Intelligent DRAM: IRAM IEEE Micro 1997; 17 (2): 33-44
- The Architecture, Operation, and Design of the Queue Management Block in the ATLAS I ATM Switch Technical Report FORTH-ICS/TR-172, Institute of Computer Science (ICS), Foundation for Research and Technology (FORTH), Heraklion, Crete, Greece 1996
Conference Proceedings
- Dynamic Management of TurboMode in Modern Multi-core Chips 2014
- Quasar: Resource-Efficient and QoS-Aware Cluster Management 2014
- Resource Efficienct Computing for Warehouse-scale Datacenters 2013
- ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems 2013
- iBench: Quantifying Interference for Datacenter Workloads 2013
- Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing 2013
- QoS-Aware Admission Control in Heterogeneous Datacenters 2013
- Enhanced Concurrency Control with Transactional NACKs 2013
- Locality-Aware Task Management for Unstructured Parallelism: A Quantitative Limit Study 2013
- Dune: Safe User-level Access to Privileged CPU Features 2012
- ECHO: Recreating Network Traffic Maps for Datacenters of Tens of Thousands of Servers 2012
- Storage I/O Generation and Replay for Datacenter Applications 2011
- Time and Cost-Efficient Modeling and Generation of Large-Scale TPCC/TPCE/TPCH 2011
- Phoenix++: Modular MapReduce for Shared-Memory Systems 2011
- Dynamic Fine-Grain Scheduling of Pipeline Parallelism 2011
- Accurate Modeling and Generation of Storage I/O for Datacenter Workloads 2011
- FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures 2010
- Making Nested Parallel Transactions Practical using Lightweight Hardware Support 2010
- EigenBench: A Simple Exploration Tool for Orthogonal TM Characteristics 2010
- The ZCache: Decoupling Ways and Associativity 2010
- Implementing and Evaluating a Model Checker for Transactional Memory Systems 2010
- Evaluating Bufferless Flow Control for On-Chip Networks 2010
- On the Energy (In)Efficiency of Hadoop Clusters 2009
- On the Energy (In)Efficiency of Hadoop Clusters 2009
- The Stanford Pervasive Parallelism Lab 2009
- Energy Dumpster Diving 2009
- Energy Dumpster Diving 2009
- Nemesis: Preventing Authentication & Access Control Vulnerabilities in Web Applications 2009
- Hardware Enforcement of Application Security Policies 2008
- A Comparison of High-Level Full-System Power Models 2008
- Real-World Buffer Overflow Protection for Userspace and Kernelspace 2008
- The OpenTM Transactional Application Programming Interface 2007
- A Low Power Front-end for Embedded Processors using a Block-aware Instruction Set 2007
- JouleSort: A Balanced Energy-Efficiency Benchmark 2007
- Raksha: A Flexible Architecture for Software Security 2007
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Executing Java programs with transactional memory
ELSEVIER SCIENCE BV. 2006: 111-129
View details for DOI 10.1016/j.scico.2006.05.006
View details for Web of Science ID 000241921200002
- Parallelizing SPECjbb2000 with Transactional Memory 2006
- Early Release: Friend or Foe 2006
- Building and Using the ATLAS Transactional Memory System 2006
- Tutorial: Transactional Programming In A Multi-core Environment 2006
- CEARCH: Cognition Enabled Architecture 2006
- The Software Stack for Transactional Memory: Challenges and Opportunities 2006
- Full-system Power Analysis and Modeling for Server Environments 2006
- Testing Implementations of Transactional Memory 2006
- RAMP: Research Accelerator for Multiple Processors 2006
- From Chaos to QoS: Case Studies in CMP Resource Management 2006
- Deconstructing Hardware Architectures for Security 2006
- Transactional Execution of Java Programs 2005
- TAPE: a Transactional Application Profiling Environment 2005
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Programming with transactional coherence and consistency (TCC)
ASSOC COMPUTING MACHINERY. 2004: 1-13
View details for Web of Science ID 000228341700003
- VIRAM-1: A Media-Oriented Vector Processor with Embedded DRAM 2004
- Transactional Memory Coherence and Consistency (TCC) 2004
- Stream Virtual Machine and Two-Level Compilation Model for Streaming Architectures and Languages 2004
- Hardware/compiler Codevelopment for an Embedded Media Processor 2001
- Lecture Notes in Computer Science edited by Chong, F., Kozyrakis, C., Oskin, M. 2001
- Exploiting On-chip Memory Bandwidth in the VIRAM Compiler 2000
- Explicitly Parallel Architectures for Memory Performance Enhancement 2000
- Vector IRAM: A Media-oriented Vector Processor with Embedded DRAM 2000
- High-Performance Architectures for Embedded Memory Systems 1999
- High-Performance Architectures for Embedded Memory Systems 1998
- Evaluation of Existing Architectures in IRAM Systems 1997
- Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control 1997
- Intellingent RAM (IRAM): the Industrial Setting, Applications, and Architectures 1997
- Intelligent RAM (IRAM): Chips that Compute and Remember 1997
- The Energy Efficiency of IRAM Architectures 1997