William Dally
Willard R. and Inez Kerr Bell Professor in the School of Engineering and Professor (Research) of Electrical Engineering
Computer Science
Bio
Dally investigates methods for applying VLSI technology to solve information processing problems. His current projects include network architecture, multicomputer architecture, media-processor architecture, and high-speed (4Gb/s) CMOS signaling. His research involves demonstrating novel concepts with working systems. Previous systems include the MARS Hardware Accelerator, the Torus Routing Chip, the J-Machine, M-Machine, and the Reliable Router. His group has pioneered techniques including fast capability-based addressing, processor coupling, virtual channel flow control, wormhole routing, link-level retry, message-driven processing, and deadlock-free routing.
Academic Appointments
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Professor-Research, Computer Science
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Professor-Research, Electrical Engineering
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Member, Bio-X
Boards, Advisory Committees, Professional Organizations
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Member, National Academy of Engineering (2013 - Present)
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Member, American Academy of Arts and Sciences (2013 - Present)
Professional Education
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PhD, Caltech (1986)
2015-16 Courses
- Green Electronics
EE 155, EE 255 (Aut) -
Independent Studies (23)
- Advanced Reading and Research
CS 499 (Aut, Win, Spr, Sum) - Advanced Reading and Research
CS 499P (Aut, Win, Spr, Sum) - Computer Laboratory
CS 393 (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390A (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390B (Aut, Win, Spr, Sum) - Curricular Practical Training
CS 390C (Aut, Win, Spr, Sum) - Independent Database Project
CS 395 (Aut, Win, Spr, Sum) - Independent Project
CS 399 (Aut, Win, Spr, Sum) - Independent Project
CS 399P (Aut, Win, Spr, Sum) - Independent Work
CS 199 (Aut, Win, Spr, Sum) - Independent Work
CS 199P (Aut, Win, Spr, Sum) - Master's Thesis and Thesis Research
EE 300 (Aut, Win, Spr, Sum) - Part-Time CPT
CS 390S (Aut) - Part-Time CPT
CS 390T (Win) - Part-Time Curricular Practical Training
CS 390Q (Spr) - Part-time Curricular Practical Training
CS 390P (Win, Spr) - Programming Service Project
CS 192 (Aut, Win, Spr, Sum) - Senior Project
CS 191 (Aut, Win, Spr, Sum) - Special Studies and Reports in Electrical Engineering
EE 191 (Aut, Win, Spr) - Special Studies and Reports in Electrical Engineering
EE 391 (Aut, Win, Spr, Sum) - Special Studies or Projects in Electrical Engineering
EE 190 (Aut, Win, Spr) - Special Studies or Projects in Electrical Engineering
EE 390 (Aut, Win, Spr, Sum) - Writing Intensive Senior Project (WIM)
CS 191W (Aut, Win, Spr)
- Advanced Reading and Research
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Prior Year Courses
2014-15 Courses
- Green Electronics
EE 152 (Aut) - Stanford's Little Box Challenge
EE 192X, EE 292X (Win, Spr)
2013-14 Courses
- Green Electronics
EE 152 (Aut)
2012-13 Courses
- Green Electronics
EE 152 (Aut)
- Green Electronics
All Publications
- Logic Simulation Algorithms for Pipelined Hardware Architectures Hardware Accelerators for Electrical CAD edited by Ambler, T., Agrawal, P. 1988.
- Program Chair’s Message
- The Reconfigurable Arithmetic Processor
- Message-Driven Processor Architecture: Verson 11
- Stanford University Concurrent VLSI Architecture Memo 124 Elastic Buffer Networks-on-Chip
- Spills, Fills, and Kills
- Conference Author/Panelist Index
- SSCS Members Honored as 2002 IEEE Fellows
- IEEE MICRO 1998 ANNUAL INDEX, VOL. 18 Burns ; 66: 79
- CIMI FÍITIIt
- AI Memo No. 1272 April 26, 1994
- ISSCC 2004/SESSION 7/TD: SCALING TRENDS/7.1
- ARVLSI’97 Committees
- ISSCC 2007/SESSION 24/MULTI-GB/s TRANSCEIVERS/24.3
- Globally Adaptive Load-Balanced Routing on k-ary n-cubes
- IEEE Fellows Lead the Engineering Profession
- 1987 INDEX, VOLUME 4
- 6 Guest Editors’ Introduction: Top Picks from the 2008 Computer Architecture Conferences Joel Emer and Dean Tullsen 10 Larrabee: A Many-Core x86 Architecture
- 2010 Reviewers List
- 5 Guest Editors’ Introduction: Hot Chips 21 Krste Asanovic and Ralph Wittig 7 Power7: IBM’s Next-Generation Server Processor
- 31st Annual International Symposium on Computer Architecture ISCA 2004
- 21st century digital design tools 2013
- A 0.54 pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2013
- A detailed and flexible cycle-accurate network-on-chip simulator Performance Analysis of Systems and Software (ISPASS) 2013
- A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications IEEE 2013
- Composition and reuse with compiled domain-specific languages 2013
- Optimizing data structures in high-level programs: new directions for extensible compilers based on staging 2013
- Channel reservation protocol for over-subscribed channels and destinations 2013
- Article 8-A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors ACM Transactions on Computer Systems-TOCS 2012; 2 (30): 38
- A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware 2012
- Digital Design: A Systems Approach Cambridge University Press. 2012
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Green-Marl: A DSL for Easy and Efficient Graph Analysis
ASPLOS XVII: SEVENTEENTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS
2012: 349-362
View details for Web of Science ID 000304281900029
- Unifying primary cache, scratch, and register file memories in a throughput processor 2012
- 4 Guest Editor’s Introduction: CPUs, GPUs, and Hybrid Computing David Brooks 7 GPUs and the Future of Parallel Computing 2011
- Guaranteeing forward progress of unified register allocation and instruction scheduling Technical Report Concurrent VLSI Architecture Group Memo 127, Stanford 2011
- Gpus and the future of parallel computing Micro, IEEE 2011; 5 (31): 7-17
- Energy-efficient mechanisms for managing thread context in throughput processors ACM SIGARCH Computer Architecture News 2011; 3 (39): 235-246
- 2011 Index IEEE Computer Architecture Letters Vol. 10 Computer Architecture Letters 2011; 53: 56
- Circuit challenges for future computing systems 2011
- Liszt: a domain specific language for building portable mesh-based PDE solvers 2011
- A compile-time managed multi-level register file hierarchy 2011
- 2010 IEEE Symposium on Asynchronous Circuits and Systems 2010
- Throughput computing 2010
- Evaluating bufferless flow control for on-chip networks 2010
- The even/odd synchronizer: A fast, all-digital, periodic synchronizer Asynchronous Circuits and Systems (ASYNC), 2010 IEEE Symposium on 2010: 75-84
- Moving the needle, computer architecture research in academe and industry ACM SIGARCH Computer Architecture News 2010; 3 (38): 1-1
- Booksim 2.0 User’s Guide Standford University 2010
- Fine-grain dynamic instruction placement for L0 scratch-pad memory 2010
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Block-Parallel Programming for Real-time Embedded Applications
2010
View details for DOI D
- Apparatus and method for packet scheduling US Patent 2010; 760 (7): 747
- The GPU Computing Era (HTML) 2010
- The GPU computing era Micro, IEEE 2010; 2 (30): 56-69
- The end of denial architecture and the rise of throughput computing Keynote speech at Desgin Automation Conference 2010
- The end of denial architecture and the rise of throughput computing 2010
- Exascale software study: Software challenges in extreme scale systems DARPA IPTO, Air Force Research Labs 2009
- Indirect adaptive routing on large scale interconnection networks ACM SIGARCH Computer Architecture News 2009; 3 (37): 220-231
- Router designs for elastic buffer on-chip networks 2009
- Power efficient supercomputing Accelerator-based Computing and Manycore Workshop (presentation) 2009; 1
- Allocator implementations for network-on-chip routers 2009
- Maximizing the Filter Rate of L0 Compiler-Managed Instruction Stores by Pinning Technical Report 126, Concurrent VLSI Architecture Group, Stanford University 2009
- Stream Processors Multicore Processors and Systems 2009: 231-270
- Load-balanced routing US Patent 2009; 633 (7): 940
- Embracing heterogeneity–parallel programming for changing hardware 2009
- Elastic-buffer flow control for on-chip networks High Performance Computer Architecture 2009
- Hierarchical instruction register organization Computer Architecture Letters 2008; 2 (7): 41-44
- A tuning framework for software-managed memory hierarchies 2008
- An energy-efficient processor architecture for embedded systems Computer Architecture Letters 2008; 1 (7): 29-32
- Exascale computing study: Technology challenges in achieving exascale systems 2008
- A programmable 512 GOPS stream processor for signal, image, and video processing Solid-State Circuits, IEEE Journal 2008; 1 (43): 202-213
- Structured Application-Specific Integrated Circuit (ASIC) Study STANFORD UNIV CA COMPUTER SYSTEMS LAB 2008
- Exascale computing study: Technology challenges in achieving exascale systems 2008
- Flattened butterfly: a cost-efficient topology for high-radix networks ACM SIGARCH Computer Architecture News 2007; 2 (35): 126-137
- Research Challenges for On-Chip Interconnection Networks (HTML) 2007
- Executing irregular scientific applications on stream architectures 2007
- A 14mW 6.25 Gb/s transceiver in 90nm CMOS for serial chip-to-chip communications 2007
- Architectural support for the stream execution model on general-purpose processors 2007
- Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy Parallel Architecture and Compilation Techniques 2007
- Interconnect-Centric Computing. HPCA 2007; 1
- Tradeoff between data-, instruction-, and thread-level parallelism in stream processors 2007
- Future directions for on-chip interconnection networks OCIN Workshop 2006
- Sequoia: programming the memory hierarchy 2006
- Multi-Core for HPC: Breakthrough or Breakdown? 2006
- Topology optimization of interconnection networks Computer Architecture Letters 2006; 1 (5): 10-13
- Prefix search method US Patent 2006; 130 (7): 847
- DRAFT Final Report: Workshop on On-and Off-Chip Networks for Multi-Core Systems Capturado em: http://www. ece. ucdavis. edu/~ ocin06 2006
- Compiling for stream processing 2006
- Data parallel address architecture Computer Architecture Letters 2006; 1 (5): 30-33
- Adaptive routing in high-radix clos network 2006
- Pulsenet-A Parallel Flash Sampler and Digital Processor IC for Optical SETI Custom Integrated Circuits Conference, 2006. CICC'06. IEEE 2006: 261-264
- Design tradeoffs for tiled CMP on-chip networks 2006
- The design space of data-parallel memory systems 2006
- Fault tolerance techniques for the merrimac streaming supercomputer 2005
- 11th International Symposium on High-Performance Computer Architecture (HPCA'05) 2005
- Globally adaptive load-balanced routing on tori Computer Architecture Letters 2004; 1 (3): 2-2
- Streams and vectors: A memory system perspective 6th WorkShop on Media and Streaming Processors 2004
- High-Speed Logic, Circuits, Libraries and Layout Closing the Gap Between ASIC & Custom 2004: 101-144
- The case for broader computer architecture education: keynote address 2004
- Buffer and delay bounds in high radix interconnection networks Computer Architecture Letters 2004; 1 (3): 8-8
- Adaptive channel queue routing on k-ary n-cubes 2004
- Stream processors: Progammability and efficiency Queue 2004; 1 (2): 52
- Principles and practices of interconnection networks Access Online via Elsevier 2004
- How scaling will change processor architecture Solid-State Circuits Conference, 2004. Digest of Technical Papers. 2004
- Exploiting Structure and Managing Wires to Increase Density and Performance Closing the Gap Between ASIC & Custom 2004: 269-287
- Analysis and performance results of a molecular modeling application on Merrimac 2004
- Space-efficient source routing 2004
- The Ninth International Symposium on High-Performance Computer Architecture (HPCA'03) 2003
- Merrimac: Supercomputing with streams 2003
- Prefix search method 2003
- A second-order semi-digital clock recovery circuit based on injection locking Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC 2003
- A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os 2003
- Methods and apparatus for event-driven routing 2003
- 0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on 2003: 63-66
- Throughput-centric routing algorithm design 2003
- CMOS high-speed I/Os-present and future 2003
- Migration in single chip multiprocessors Computer Architecture Letters 2002; 1 (1): 12-12
- Locality-preserving randomized oblivious routing on torus networks 2002
- Comparing Reyes and OpenGL on a stream architecture 2002
- Prefix search circuitry and method 2002
- Internet switch router 2002
- Computer architecture is all about interconnect High-Perf. Comp. Architecture 2002
- Worst-case traffic for oblivious routing functions 2002
- Stream Processing for High-Performance Embedded Systems Defense Technical Information Center 2002
- Method and system for guaranteeing quality of service in large capacity input output buffered cell switch based on minimum bandwidth guarantees and weighted fair share of unused bandwidth 2002
- Worst-case Traffic for Oblivious Routing Functions (PDF) 2002
- A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips 2002
- Guest Editors' Introduction: Hot Chips 12 (HTML) 2001
- Elastic interconnects: Repeater-inserted long wiring capable of compressing and decompressing data 2001
- Monolithic chaotic communications system Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International 2001
- Guest Editors' Introduction: Hot Chips 12 IEEE MICRO 2001; 2 (21): 0013-15
- Scalable switching fabrics for Internet routers White paper, Avici Systems Inc 2001
- A streaming supercomputer Whitepaper 2001
- A single-chip terabit switch Hot Chips 2001; 13
- A Delay Model for Router Microarchitectures (HTML) 2001
- Smart memories: A modular reconfigurable architecture ACM SIGARCH Computer Architecture News 2000; 2 (28): 161-171
- Flit-reservation flow control 2000
- Stream Scheduling STANFORD UNIV CA COMPUTER SYSTEMS LAB 2000
- 10 Subspace Optimizations edited by Kessler, Christoph, W. 2000
- Stream scheduling STANFORD UNIV CA COMPUTER SYSTEMS LAB 2000
- Sixth International Symposium on High-Performance Computer Architecture 2000
- Memory access scheduling isca 2000; 128
- Register organization for media processing 2000
- Polygon rendering on a stream architecture 2000
- A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation 2000
- Sixth International Symposium on High-Performance Computer Architecture 2000
- Computer Architecture for the Next Millenium 1999
- GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link 1999
- Interconnect-limited VLSI architecture Interconnect Technology, 1999. IEEE International Conference 1999: 15-17
- 20th Anniversary Conference on Advanced Research in VLSI 1999
- Point sample rendering Massachusetts Institute of Technology 1998
- VLSI datapath choices: Cell-based versus full-custom Massachusetts Institute of Technology 1998
- Tomorrow’s Computing Engines keynote speech, Fourth Int’l Symp. High-Performance Computer Architecture 1998
- The j-machine: A retrospective Retrospective in 1998: 54-58
- An efficient, protected message interface Computer 1998; 11 (31): 69-75
- Digital systems engineering Cambridge university press 1998
- Architecture of a message-driven processor 25 years of the international symposia on Computer architecture (selected 1998
- Architecture of the Avici terabit switch/router 1998
- Digital Systems Engineering Cambridge University Press. 1998
- E cient, protected message interface in the MIT M-Machine IEEE Computer Special Issue on Design Challenges for High-Performance 1998
- An instruction scheduling algorithm for communication-constrained microprocessors Massachusetts Institute of Technology 1998
- The Fifth International Conference on Massively Parallel Processing Using Optical Interconnections 1998
- Point sample rendering Rendering Techniques 1998; 98: 181-192
- Media Processors 1999 (Proceedings Volume) 1998
- Media processing using streams Electronic Imaging 1998: 122-134
- The J-Machine ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE 1998; 25: 54-58
- Retrospective: the J-machine 1998
- Invited Talks 1998
- Message-driven dynamics Massachusetts Institute of Technology 1997
- Transmitter equalization for 4-Gbps signaling Micro, IEEE 1997; 1 (17): 48-56
- The m-machine multicomputer International Journal of Parallel Programming 1997; 3 (25): 183-212
- The delta tree: An object-centered approach to image-based rendering 1997
- Extended ephemeral logging: log storage management for applications with long lived transactions ACM Transactions on Database Systems (TODS) 1997; 1 (22): 1-42
- Design of the Configuration and Diagnostic Units of the MAP Chip Massachusetts Institute of Technology 1997
- An I/O port controller for the MAP chip Massachusetts Institute of Technology, Dept. of Electrical Engineering and 1997
- Asynchronous event handing Massachusetts Institute of Technology 1997
- Advances in the M-machine runtime system Massachusetts Institute of Technology 1997
- TPDS Now Online! z Special Issue Editors Old and New IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1997; 3 (8): 225
- Circuit designs for the MAP chip Massachusetts Institute of Technology 1997
- 1997Annual Index, Vol. 17 development [single chip microprocessors] 1997; 2000: 28-36
- Flexible Memory Systems.(AASERT Fellowship). MASSACHUSETTS INST OF TECH CAMBRIDGE 1996
- The subspace model: Shape-based compilation for parallel systems Massachusetts Institute of Technology 1996
- Architects Look to Processors of Future MICROPROCESSOR REPORT, MICRODESIGN RESOURCES 1996; 10 (10)
- Multiprocessor coupling system with integrated compile and run time scheduling for parallelism US Patent 1996; 574 (5): 939
- Bandwidth, Granularity, and Mechanisms: Key Issues in the Design of Parallel Computers 1996
- Flexible Memory Systems.(AASERT Fellowship) MASSACHUSETTS INST OF TECH CAMBRIDGE 1996
- A data-driven IDCT architecture for low power video applications 1996
- Evaluating the locality benefits of active messages ACM SIGPLAN Notices 1995; 8 (30): 189-198
- Thread prioritization: A thread scheduling mechanism for multiple-context parallel processors Future Generation Computer Systems 1995; 6 (11): 503-518
- The M-Machine Multicomputer MASSACHUSETTS INST OF TECH CAMBRIDGE ARTIFICIAL INTELLIGENCE LAB 1995
- 1st IEEE Symposium on High-Performance Computer Architecture 1995
- Low-latency plesiochronous data retiming 1995
- Implementation of atomic primitives on distributed shared memory multiprocessors 1995
- The M-Machine operating system Massachusetts Institute of Technology 1995
- The subspace model: A theory of shapes for parallel systems 1995
- Fault tolerant adaptive routing in multicomputer networks Massachusetts Institute of Technology 1995
- The named-state register file: Implementation and performance 1995
- Proceedings 1995
- 1st IEEE Symposium on High-Performance Computer Architecture 1995
- Issues in the Design and Implementation of Instruction Processors for Multicomputers (Position Statement) Multithreaded Computer Architecture 1994: 79-82
- The implementation of a reliable router chip Massachusetts Institute of Technology 1994
- The design of a high performance SPARC bus interface Massachusetts Institute of Technology 1994
- Efficient message subsystem design Massachusetts Institute of Technology 1994
- VLSI design for freshmen and sophomores Massachusetts Institute of Technology 1994
- Subspace optimizations Automatic Parallelization 1994: 153-176
- M-Machine Microarchitecture v1. 11 1994
- Logging and recovery in a highly concurrent database 1994
- The reliable router: A reliable and high-performance communication substrate for parallel computers Parallel Computer Routing and Communication 1994: 241-255
- Named state and efficient context switching Multithreaded Computer Architecture 1994: 201-212
- Multithreaded computer architecture Boston: Kluwer Academic Publishers 1994
- Architecture and implementation of the Reliable Router 1994
- A subspace optimizing data parallel complier Massachusetts Institute of Technology 1994
- A numerical engine for distributed sparse matrices Massachusetts Institute of Technology 1994
- The design and implementation of an actor language based on linear logic Massachusetts Institute of Technology 1994
- How to Choose the Grain Size of a Parallel Computer MIT/LCS Technical Report 1994: MIT-LCS-TR-739
- XEL: extended ephemeral logging for log storage management 1994
- Hardware support for fast capability-based addressing ACM SIGPLAN Notices 1994; 11 (29): 319-327
- Deadlock-free adaptive routing in multicomputer networks using virtual channels Parallel and Distributed Systems, IEEE Transactions 1993; 4 (4): 466-475
- The J-machine multicomputer: an architectural evaluation ACM SIGARCH Computer Architecture News 1993; 2 (21): 224-235
- Performance evaluation of ephemeral logging ACM SIGMOD Record 1993; 2 (22): 187-196
- Evaluation of mechanisms for fine-grained parallel programs in the J-machine and the CM-5 ACM SIGARCH Computer Architecture News 1993; 3 (21): 302-313
- COSMOS: An operating system for a fine-grain concurrent computer Research directions in concurrent object-oriented programming 1993: 452-476
- The J-Machine architecture and evaluation Compcon Spring'93, Digest of Papers. 1993: 183-188
- Message-driven processor in a concurrent computer US Patent 1993; 212 (5): 778
- A Video Controller and Distributed Frame Bu er for the J-Machine 1993
- A universal parallel computer architecture New Generation Computing 1993; 3-4 (11): 227-249
- High-performance bidirectional signalling in VLSI systems 1993
- Mechanisms for parallel computers Parallel Computing on Distributed Memory Multiprocessors 1993: 3-25
- The Future of Computing is Parallel Computer Science Department 1993
- The J-machine: a fine-grain parallel computer Computing Systems in Engineering 1992; 1 (3): 7-15
- Design and implementation of the Message-Driven Processor 1992
- The message-driven processor: A multicomputer processing node with efficient mechanisms Micro, IEEE 1992; 2 (12): 23-39
- The message driven processor: An integrated multicomputer processing element Computer Design: VLSI in Computers and Processor 1992
- Processor coupling: Integrating compile time and runtime scheduling for parallelism ACM SIGARCH Computer Architecture News 1992; 2 (20): 202-213
- INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE 1992 Scientific information bulletin 1992; 4 (17): 35
- Custom integrated circuits Custom Integrated Circuits 1992
- A fast translation method for paging on top of segmentation Computers, IEEE Transactions 1992; 2 (41): 247-250
- MDP design tools and methods Computer Design: VLSI in Computers and Processors 1992: ICCD'92
- Virtual-Channel Flow Control (PDF) 1992
- The J-machine network Computer Design: VLSI in Computers and Processors 1992
- Pi: a parallel architecture interface Frontiers of Massively Parallel Computation, 1992., Fourth Symposium on the… 1992
- Virtual-channel flow control Parallel and Distributed Systems, IEEE Transactions 1992; 2 (3): 194-205
- Experiences Implementing Dataflow on a General-Purpose Parallel Computer. ICPP 1991; 2: 231-235
- A mechanism for efficient context switching Computer Design: VLSI in Computers and Processors 1991: ICCD'91
- Express cubes: improving the performance of< e1> k</e1>-ary< e1> n</e1>-cube interconnection networks Computers, IEEE Transactions 1991; 9 (40): 1016-1023
- Experiments with Dataflow on a General-Purpose Parallel Computer. MASSACHUSETTS INST OF TECH CAMBRIDGE ARTIFICIAL INTELLIGENCE LAB 1991
- Experiments with data flow on a general-purpose parallel computer. Memorandum report Massachusetts Inst. of Tech., Cambridge, MA (United States). Artificial 1991
- Experiments with Dataflow on a General-Purpose Parallel Computer MASSACHUSETTS INST OF TECH CAMBRIDGE ARTIFICIAL INTELLIGENCE LAB 1991
- System design of the J-Machine 1990
- Experience with concurrent aggregates (CA): Implementation and programming 1990
- Advanced Research in VLSI: Proceedings of the Sixth MIT Conference;[papers Presented at the Sixth MIT Conference on Advanced Research in VLSI, Held in Cambridge, Mass., in 1990] 1990
- The Message-Driven Processor: A Multicomputer Processing Node with E cient Mechanisms 1990
- Performance analysis of< e1> k</e1>-ary< e1> n</e1>-cube interconnection networks Computers, IEEE Transactions 1990; 6 (39): 775-785
- Network and processor architecture for message-driven computers VLSI and Parallel Computation 1990: 140-222
- Critical Problems in Very Large Scale Computer Systems MASSACHUSETTS INST OF TECH CAMBRIDGE 1990
- Concurrent aggregates (CA) ACM Sigplan Notices 1990; 3 (25): 187-196
- Virtual-channel flow control 1990
- Proceedings of the sixth MIT conference on Advanced research in VLSI 1990
- Simultaneous bidirectional signalling for IC systems Computer Design: VLSI in Computers and Processors 1990: ICCD'90
- Critical Problems in Very Large Scale Computer Systems KURTZ LABS YELLOW SPRINGS OH 1990
- A hardware logic simulation system Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions 1990
- Express cubes: Improving the performance of k-ary n-cube interconnection networks MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE 1989
- Algorithms for accuracy enhancement in a hardware logic simulator 1989
- Universal mechanisms for concurrency PARLE'89 Parallel Architectures and Languages Europe 1989: 19-33
- Experience with CST: Programming and Implementation MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1989
- A fine-grain, message-passing processing node Concurrent Computations 1989: 375-389
- The J-machine: a fine grain concurrent computer MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1989
- Micro-optimization of floating-point operations ACM SIGARCH Computer Architecture News 1989; 2 (17): 283-289
- Experience with CST: Programming and implementation ACM SIGPLAN Notices 1989; 7 (24): 101-109
- A network element based fault tolerant processor Massachusetts Institute of Technology 1988
- Finite-grain message passing concurrent computers 1988
- The J-machine: System support for Actors MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1988
- ON FIFTH GENERATION COMPUTER SYSTEMS 1988, edited by ICOT.© ICOT, 1988 1988; 3 (FGCS'88): 154
- Object-Oriented Concurrent Programming in CST MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1988
- Message-Driven Processor architecture, Version 11. Artificial intelligence memo Massachusetts Inst. of Tech., Cambridge (USA). Artificial Intelligence Lab. 1988
- Message-Driven Processor Architecture MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1988
- Critical Problems in Very Large Scale Computer Systems MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1988
- Critical problems in very-large-scale computer systems. Semiannual technical report, 1 April-30 September 1988 Massachusetts Inst. of Tech., Cambridge (USA). Microsystems Research Center 1988
- Object-oriented concurrent programming in CST 1988
- The reconfigurable arithmetic processor ACM SIGARCH Computer Architecture News 1988; 2 (16): 30-36
- Mechanisms for Concurrent Computing FGCS 1988: 154-156
- The Reconfigurable Arithmetic Processor MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1988
- The Balanced Cube A VLSI Architecture for Concurrent Data Structures 1987: 27-73
- Architecture and design of the MARS hardware accelerator 1987
- Performance analysis of k-ary n-cube interconnection networks NASA STI/Recon Technical Report N 1987; 88: 30010
- MARS: A multiprocessor-based programmable accelerator Design & Test of Computers, IEEE 1987; 5 (4): 28-36
- Graph Algorithms A VLSI Architecture for Concurrent Data Structures 1987: 75-132
- Deadlock-free message routing in multiprocessor interconnection networks Computers, IEEE Transactions 1987; 5 (100): 547-553
- A coherent VLSI environment Massachusetts Inst. of Tech. Report 1987
- Concurrent Smalltalk A VLSI Architecture for Concurrent Data Structures 1987: 13-25
- A message passing system for a fault tolerant parallel processor Massachusetts Institute of Technology 1987
- A Coherent VLSI Design Environment MASSACHUSETTS INST OF TECH CAMBRIDGE 1987
- Design of a self-timed VLSI multicomputer communication controller NASA STI/Recon Technical Report 1987; 88: 30014
- Coherent VLSI environment. Semiannual technical report, 1 October 1986-31 March 1987 Massachusetts Inst. of Tech., Cambridge (USA). Microsystems Research Center 1987
- A coherent VLSI design environment MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1987
- Architecture of a Message-Driven Processor MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1987
- A Coherent VLSI Design Environment MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1987
- Concurrent computer architecture Massachusetts Inst. of Tech., Cambridge (USA). Artificial Intelligence Lab. 1987
- The torus routing chip Distributed computing 1986; 4 (1): 187-196
- On the Performance of k-ary n-cube Interconnection Networks California Institute of Technology 1986
- 5208: TR: _86 1986
- The torus routine chip 1986
- A High-performance VLSI Quaternary Serial Multiplier 1986
- Wire-efficient VLSI multiprocessor communication networks Massachusetts Institute of Technology, Microsystems Program Office 1986
- Directions in concurrent computing 1986
- A Coherent VLSI Design Environment MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER 1986
- VLSI architecture for concurrent data structures California Inst. of Tech. 1986
- Concurrent Algorithms for the Max-Flow Problem California Institute of Technology 1985
- A hardware architecture for switch-level simulation Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions 1985
- The balanced cube: a concurrent data structure California Institute of Technology 1985
- Fungicides for Crop Protection: Invited papers International Specialized Book Service Incorporated 1985
- An object oriented architecture ACM SIGARCH Computer Architecture News 1985; 3 (13): 154-161
- The MOSSIM Simulation Engine Architecture and Design California Institute of Technology 1984
- A Special Purpose Processor for Switch-Level Simulation International Conference on Computer Aided Design 1984