Ultra Low Power Technology Group

The Ultra Low Power Technology Group in the Department of Electrical Engineering at Stanford University is interested in the study and implementation of VLSI processing that is both low-power and high-performance.

This is done through the radical reduction of supply voltages using chips fabricated in tunable low threshold CMOS processes. Current designs are expected to operate in excess of 100MHz with supply voltages below 500mV at room temperature. Fabricated chips have operated error-free at supply voltages of 125mV with ring oscillators operating at Vdd=70mV at room temperature and Vdd=27mV at 77K.

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ULP Chip Gallery

Group Projects

SPIFFEE, an energy-efficient single-chip 1024-point FFT processor.
STARP motion estimation chip chip photo (155KB gif)
ULPM: 32bit x 32bit ULP Multiplier die photo (206KB)
Srambb: a 128 x 36bit low-power SRAM. A few slides (596KB compressed ps)
ULP Accumulator 1: a low-voltage memory/adder test chip. Chip plot (55KB compressed ps)
ULP Accumulator 2: a low-voltage memory/adder test chip. A few slides (586KB compressed ps)
Multbb: a 20bit pipelined full-array multiplier.

Internal web page

Last update: August 30, 2000.

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