Robert Dutton

All Publications

• New Challenges in Device Design for Integrated Electronic Systems Dutton, R., W., Yu, Z.
• Proc. of the ICSSDP Simulation of Multilayer Structures for VLSI Using the SUPREM-III Process Simulation Program Hansen, S., E., Shott, J., D., Fahey, P., M., Plummer, J., D., Dutton, R., W., K. edited by R.J., Board, D. Pineridge Press.
• Simulation of Integrated Circuits Design Process and Device Modeling for Integrated Circuit Design Antoniadis, D., A., Dutton, R., W.
• Analysis of Advanced Devices Using Industry-Networked Technology CAD (ALADDIN-CAD) Final Report, California Competitive Technology Program (CompTech Grant # C90-072). Dutton, R., W.
• Workload Dependent NBTI and PBTI Analysis for a Sub-45nm Commercial Microprocessor IEEE IRPS, Anaheim, CA Mintarno, E., Chandra, V., Pietromonaco, D., Aitken, R., Dutton, R., W. 2013: 3A.1.1-3A.1.6
• Applications of NanoNewton Dielectrophoretic Forces using Atomic Layer Deposited Oxides for Microfluidic Sample Preparation and Proteomics Emaminejad, S., Javanmare, M., Gupta, C., Dutton, R., W., Davis, R., W., Howe, R., T. 2013
• Smart surfaces: Use of electrokinetics for selective modulation of biomolecular affinities Emaminejad, S., Javanmard, M., Dutton, R., W., Davis, R., W. 2012
• Efficient Control of DNA Transport in Nanopore-based Nanofluidic Transistors Paik, K., H., Liu, Y., Tabard-Cossa, V., Huber, D., Provine, J., Howe, R., Dutton, R. W. 2011
• An Electronic Microfluidic Switch using Dielectrophoresis for Control of Microparticles Javanmard, M., Emaminejad, S., Dutton, R., W., Davis, R. 2011
• Smart Surfaces: Use of Electrokinetics for Selective Modulation of Biomolecular Affinities MRS Fall Meeting, Boston, MA Emaminejad, S., Javanmard, M., Dutton, R., W., Davis, R., W. 2011; 1414
• Field Effect Resistor, a Single-Device-at-Pad Solution for ESD Protection in Deeply Scaled SOI Technology Cao, S., Salman, A., A., Chun, J., H., Beebe, S., G., Pelella, M., M., Dutton, R., W. 2010
• Modeling and RF Analysis of Silicon Inter-band Tunnel Diode with THz Cut-off Frequency Kim, K., R., Kang, I., M., Dutton, R., W. 2010
• Investigation on Output Driver with Stacked Devices for ESD Design Window Engineering Cao, S., Chun, J., H., Choi, E., Beebe, S., Anderson, W., Dutton, R., W. 2010
• Optimized Self-Tuning for Circuit Aging Mintarno, E., Skaf, J., Zheng, R., Velamala, J., Cao, Y., Boyd, S., Dutton, R. W. 2010
• Electrical Modulation of Ion Concentration in Dual-Gated Nanochannels Liu, Y., Ran, Q., Dutton, R., W. 2010
• ESD Design Challenges and Strategies in Deeply-Scaled Integrated Circuits Cao, S., Chen, T., W., Beebe, S., G., Dutton, R., W. 2009
• Field Effect Diode for Effective CDM ESD Protection in 45nm SOI Technology Cao, S., Beebe, S., G., Salman, A., A., Pelella, M., M., Chun, J, H., Dutton, R., W. 2009
• Numerical Flicker Noise Model for Dual Channel FETs Chen, C., Y., Liu, Y., Dutton, R., W., Sato-Iwanaga, J., Inoue, A., Sorada, H. 2009
• The Role of Surface Charge and Binding Properties in Silicon-Based Field Effect Nanowire Biosensors Transducers 2009, Denver, CO Liu, Y., Dutton, R., W. 2009: 1678-1681
• Modeling and Simulation of Orientation-Dependent Fluctuations in Nanowire Field-Effect Biosensors Using the Stochastic Linearized Poisson-Boltzmann Equation Heitzinger, C., Ringhofer, C., Liu, Y., Dutton, R., W. 2009
• Lateral Ge/SiGe/Si Hetero-channel p-Type MOSFETs Chen, C., Y., Liu, Y., Kim, J., Dutton, R., W. 2009
• Double-Well Field Effect Diode vs. SCR Behavior under CDM Stress in 45nm SOI Technology Salman, A., A., Cao, S., Beebe, S., G., Pelella, M., M., Dutton, R., W. 2008
• Overcoming the Screen-induced Performance Limits of Nanowire Biosensors: A Simulation Study on the Effect of Electro-Diffusion Flow Liu, Y., Lilja, K., Heitzinger, C., Dutton, R., W. 2008
• Progress in Biosensor and Bioelectronics Simulations: New Applications for TCAD Hassibi, A., Liu, Y., Dutton, R., W. 2008
• Effect of Electrodiffusion Current Flow on Electrostatic Screening in Aqueous Pores J. Appl. Phys. Liu, Y., Sauer, J., Dutton, R., W. 2008; 8 (103)
• An Effective Algorithm for Numerical Schrodinger Solver of Quantum Well Structures Journal of Computational Electronics Kim, J., Chen, C., -Y., Dutton, R., W. 2008; 1 (7): 1-5
• Foreword Special Issue on Simulation and Modeling of Nanoelectronics Devices IEEE Trans. Electron Devices Sangiorgi, E., Asenov, A., Bennett, H., S., Dutton, R., W., Esseni, D., Giles, M., D. 2007; 9 (54): 2072 - 2078
• A Circuit-Based Noise Parameter Extraction Technique for MOSFETs Navid, R., Lee, T., H., Dutton, R., W. 2007
• Macro-model for post-breakdown 90nm and 130nm transistors and its applications in predicting chip-level function failure after ESD-CDM events 2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL Chen, T. W., Ito, C., Loh, W., Wang, W., Mitra, S., Duttona, R. W. 2007: 78-85

  View details for Web of Science ID 000246989600013

• Thermal Modeling and Device Noise Properties of 3D-SOI Technology Chen, T., W., Chun, J., H., Lu, Y., C., Navid, R., Wang, W., Dutton, R., W. 2007
• Electro-Thermal, Transient, Mixed-Mode 2D Simulation Study of SiC Power Thyristors Operating Under Pulsed-Power Conditions Hillkirk, L., M., Hefner, A., R., Dutton, R., W., Bayne, S., B., O'Brien, H. 2007
• Gate Oxide Reliability Characterization in the 100ps Regime with Ultra-fast Transmission Line Pulsing System Chen, T., W., Ito, C., Maloney, T., Loh, W., Dutton, R., W. 2007
• Simulation of p-n Junction Properties of Nanowires and Nanowire Arrays Hu, J., Liu, Y., Maslov, A., Ning, C, Z., Dutton, R., W., Kang, S. M. 2007
• RF ESD Protection Strategies: Codesign vs. Low-C Protection Microelectronics Reliability Soldner, W., Streibl, M., Hodel, U., Tiebout, M., Gossner, H., Schmitt-Landsiedel, D., Dutton, R. W. 2007; 7 (47): 1008-1015
• Physics-based Numerical Simulation for Design of High-voltage, Extremely-high Current Density SiC Power Devices Hillkirk, L., M., Hefner, A., R., Dutton, R., W. 2007
• A Simple Technique for the Monte Carlo Simulation of Transport in Quantum Wells Kim, J., Chen, C., Y., Dutton, R., W. 2007
• Modeling and Measurements of Electrical and Thermal Memory Effects for RF power LDMOS Tornblad, O., Wu, B., Dai, W., Blair, C., Ma, G., Dutton, R., W. 2007
• Simulations of Flicker Noise in SiGe HMOS: Body Bias Dependence SASIMI, Sapporo, Japan Chen, C., Y., Liu, Y., Dutton, R., W., Sato-Iwanaga, J., Inoue, A., Sorada, H. 2006: 238-241
• Silencer Pro: A Synthesized Compact Models-Enabled CAD Tool for Substrate Noise Analysis SASIMI, Nagoya, Japan Lan, H., MacClary, M., Mayaram, K., Fiez, T., S., Dutton, R., W. 2006
• Modeling of Charge Trapping Induced Threshold-Voltage Instability in High-k Gate Dielectric FETs IEEE Electron Dev. Lett Liu, Y., Shanware, A., Colombo, L., Dutton, R., W. 2006; 6 (27): 489-491
• Numerical Simulation of Field-Induced Inter-Band Tunneling Effect Transistor Using TCAD-Based Device Simulator 64th Device Research Conference, State College, PA Kim, K., R., Park, B., G., Dutton, R., W. 2006: 119-120
• Numerical Investigation of Low Frequency Noise in MOSFETs with High-k Gate Stacks IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Monterey, CA Liu, Y., Cao, S., Dutton, R., W. 2006: 99-102
• Device Analysis of Linearity in RF Power Devices by Harmonic Balance Device Simulation Tornblad, O., Ma, G., Dutton, R., W. 2006
• A Frequency-Domain VFTLP Pulse Characterization Methodology and Its Application to CDM ESD Modeling Ito, C., Loh, W., Chen, T., W., Dutton, R., W. 2006
• Erratum: “Comprehensive Study of Noise Processes in Electrode Electrolyte Interfaces” [J. Appl. Phys. 96, 1074 (2004)] J. Appl. Phys. Hassibi, A., Navid, R., Dutton, R., W., Lee, T., H. 2005; 6 (98)
• Coupled Optical and Electronic Simulations of Electrically Pumped Photonic-Crystal-Based LEDs Veronis, G., Liu, Y., Suh, W., Han, M., Wang, Z., Dutton, R., W. 2005
• Coupled Electron-Phonon Transport in Nanometer-Scale Silicon Devices SRC TechCon, Portland OR Rowlette, J., Pop, E., Sinha, S., Dutton, R., W., Goodson, K., E. 2005
• Joule heating under quasi-ballistic transport conditions in bulk and strained silicon devices SISPAD: 2005 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES Pop, E., Rowlette, J. A., DUTTON, R. W., Goodson, K. E. 2005: 307-310

  View details for Web of Science ID 000234260200076

• Synthesized Compact Model and Experimental Results for Substrate Noise Coupling in Lightly Doped Processes Lan, H., Chen, T., W., Chui, C., O., Nikaeen, P., Kim, J., W., Dutton, R., W. 2005
• Modeling and Simulation of Jitter in Phase-Locked Loops due to Substrate Noise Kim, J., W., Lu, Y., C., Dutton, R., W. 2005
• Linearity Analysis of RF LDMOS Devices Utilizing Harmonic Balance Device Simulation Tornblad, O., Ito, C., Rotella, F., Ma, G., Dutton, R., W. 2005
• Electro-Thermal Simulations of Nanoscale Transistors with Optical and Acoustic Phonon Head Conduction Chun, J., H., Kim, B., Liu, Y., Tornblad, O., Dutton, R., W. 2005
• Effects of Local Electric Field and Effective Tunnel Mass on the Simulation of Band-to-band Tunnel Diode Model Kim, K., R., Dutton, R., W. 2005
• A New Method for Sensitivity Analysis of Photonic Crystal Devices Veronis, G., Dutton, R., W., Fan, S. 2005
• Small-Signal Modeling of RF CMOS IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Munich, Germany Jang, J., Dutton, R., W. 2004
• Effects of Scaling on the SNR and Speed of Biosensors Hassibi, A., Lee, T., H., Navid, R., Dutton, R., W., Zahedi, S. 2004
• New Capabilities for Verilog-A Implementations of Compact Device Models Nanotech, Boston, MA Mierzwinski, M., O’Halloran, P., Troyanovsky, B., Mayaram, K., Dutton, R., W. 2004
• Electro-thermal comparison and performance optimization of thin-body SOI and GOI MOSFETs Pop, E., Chui, C. O., Sinha, S., Dutton, R., Goodson, K. IEEE. 2004: 411-414

  View details for Web of Science ID 000227158500093

• Compact Modeling and Experimental Verification of Substrate Resistance in Lightly Doped Substrates Lan, H., Chen, T., W., Chui, C., O., Dutton, R., W. 2004
• Technology Limits and Compact Model for SiGe Scaled FETs Nanotech, Boston, MA Dutton, R., W., Choi, C, H. 2004
• Synthesized Compact Models (SCM) for Substrate Noise Coupling in Mixed-Signal Ics Design, Automation and Test in Europe 2004 (DATE ’04), CNIT La Defence, Paris, France Lan, H., Dutton, R., W. 2004: 836-841
• Realization of Digital Noise Emulator for Characterization of Systems Exposed to Substrate Noise SASIMI, Kanazawa, Japan Lu, Y., C., Kim, J., W., Nakano, N., Colleran, D., Yue, P., Dutton, R., W. 2004
• Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design ISQED, San Jose, CA Veronis, G., Lu, Y, C., Dutton, R., W. 2004: 303-308
• Electro-thermal Simulations of Strained-Si MOSFETs under ESD Conditions Chun, J, H., Choi, C, H., Dutton, R., W. 2004
• Close-in Phase Noise in Electrical Oscillators Navid, R., Jungemann, C., Lee, T., Dutton, R., W. 2004
• A PMOSFET ESD Failure Caused by Localized Charge Injection Chun, J., H., Duvvury, C., Boselli, G., Kunz, H., Dutton, R., W. 2004
• Reprogrammable, Wide Tuning Range 1.6GHz CMOS VCO with Low Phase Noise Variation Papalias, T., A., Lee, T., T., Hajimiri, A., Dutton, R., W., Lee, T., H. 2004
• Synthesized Compact Models for Mixed Signal Design and Noise Analysis AFRA/SNDM NeoCAD Final Report Dutton, R., W., Kim, J., W., Lan, H., Lu, Y, C. 2004
• Accurate small-signal model and its parameter extraction in RF silicon MOSFETs 2003 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3 Jang, J. J., Yu, Z. P., DUTTON, R. W. 2003: 2109-2111

  View details for Web of Science ID 000184045100545

• Implementation of Temperature Dependent Contact Resistance Model for the Analysis of Deep Submicron Devices under ESD Chun, J., H., Liu, Y., Duvvury, C., Dutton, R., W. 2003
• A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design Lan, H., Yu, Z., Dutton, R., W. 2003
• Algorithm for Evaluating Nodal Vector Quantities in Device Simulation and its Applications to Modeling Quantum Mechanical Effects in Sub-50nm MOSFETs Yu, Z., Yergeau, D., W., Dutton, R., W. 2003
• Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductance Interconnect Technology and Design for Gigascale Integration Qi, X., Dutton, R., W. edited by Davis, J., Meindl, J., D. Kluwer Academic Publishers. 2003: 1
• Implications of Gate Tunneling and Quantum Effects on Compact Modeling in the Gate-Channel Stack NanoTech Dutton, R., W., Choi, C, H. 2003
• Detailed heat generation simulations via the Monte Carlo method 2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES Pop, E., Dutton, R., Goodson, K. 2003: 121-124

  View details for Web of Science ID 000185660800030

• Hydrodynamic Modeling of RF Noise in CMOS Devices Jungemann, C., Neinhus, B., Nguyen, C., D., Meinerzhagen, B., Dutton, R., W., Scholten, A., J. 2003
• Efficient Techniques for Reducing Substrate Model Complexity in Mixed-Signal IC’s Lan, H., Lu, Y., Nakano, N., Dutton, R., W. 2003
• Lumped, Inductorless Oscillators: How Far Can They Go Navid, R., Lee, T., H., Dutton, R., W. 2003
• Compact Modeling and Design Using Ultra-thin SOI Devices-Implications of Gate Tunneling and Quantum Effects Dutton, R., W., Choi, C., H. 2003
• Circuit Impact of Gate Leakage and Thermal Modeling for Ultra-scaled MOS Devices Dutton, R., W., Pop, E., Choi, C, H. 2003
• Behavioral Simulation Techniques for Substrate Noise Analysis in PLL Circuits Kim, J., W., Perrott, M., H., Dutton, R., W. 2003
• Characterization of Zener-Tunneling Drain Leakage Current in High-Dose Halo Implants Choi, C., H., Yang, S., H., Pollack, G., Ekbote, S., Chiadambaram, P., R., Johnson, S., Dutton, R. W. 2003
• Investigation of Thermal Breakdown Mechanism in 0.13/spl mu/m Technology ggNMOS under ESD Condition Hillkirk, L., M., Chun, J., Dutton, R., W. 2003
• Hydrodynamic Simulation of RF Noise in Deep-submicron MOSFETs Oh, T-Y., Jungemann, C., Dutton, R., W. 2003
• Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability Oh, K-H., Chun, J., Banerjee, K., Duvvury, C., Dutton, R., W. 2003
• Monte Carlo Simulation of Heat Generation in Silicon Nano-Devices SRC TechCon, Dallas, TX Pop, E., Goodson, K., Dutton, R., W. 2003
• Device Design of SiGe HBTs with Low Distortion Characteristics using Harmonic Balance Device Simulator Sato-Iwanaga, J., Asai, A., Takagi, T., Tanabe, M., Yu, Z., Dutton, R., W. 2003
• Thermal Analysis of Ultra-Thin Body Device Scaling [SOI and FinFet Devices] IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Pop, E., Goodson, K., Dutton, R., W. 2003: 36.6.1-36.6.4
• Analysis of Gate Bias Induced Heating Effects in Deep Submicron ESD Protection Designs IEEE Trans. on Device and Materials Reliability Oh, K., H., Duvvury, C., Banerjee, K., Dutton, R., W. 2002; 2 (2): 36-42
• AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections Oh, T, Y., Yu, Z., Dutton, R., W. 2002
• Performance Improvement in Larger RF LDMOSFET Power Amplifiers Ito, C., Fujioka, T., Yoshida, I., Dutton, R., W. 2002
• Hot-Carrier Energy Distribution Model and its Application to the MOSFET Substrate Current Lee, C., Jin, G., Lee, K., Kong, J., Lee, W., Rho, Y., Dutton, R. W. 2002
• The Physical Phenomena Responsible for Excess Noise in Short-Channel MOS Devices Navid, R., Dutton, R., W. 2002
• Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors Oh, K-H., Duvvury, C., Banerjee, K., Dutton, R., W. 2002
• Non-Uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Oh, K, H., Banerjee, K., Duvvury, C., Dutton, R., W. 2002: 341-344
• An OO-PDE Solver for TCAD Apps IEEE Potentials Yergeau, D., W., Dutton, R., W., Goosens, R., J. G. 2002; 2 (21): 25-29
• Two-dimensional polysilicon quantum-mechanical effects in double-gate SOI INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST Choi, C. H., Yu, Z. P., DUTTON, R. W. 2002: 723-726

  View details for Web of Science ID 000185143400166

• Series Resistance Calculation for Source/Drain Extension Using 2-D Device Simulation IEEE Trans. Electron Devices Kwong, M., Y., Choi, C., -H., Kasnavi, R., Griffin, P., Dutton, R., W. 2002; 7 (49): 1219-1226
• Accurate Model of Metal-Insulator-Semiconductor Interconnects Wang, G., Qi, X., Yu, Z., Dutton, R., W. 2002
• What Can Computer Aided Engineering Do for the SOC Era? Masuda, H., Orlowski, M., Dutton, R., W., Fukuma, M., Lee, S., W., Schoenmaker, W. 2002
• Nanoscale Heat Generation in Silicon via the Monte Carlo Method Pop, E., Sinha, S., Dutton, R., W., Goodson, K. 2002
• Analytical Analysis of Short-Channel Effects in MOSFETs for sub-100nm Technology Electronics Letters Park, J, S., Lee, S. Y., Shin, H., Dutton, R., W. 2002; 20 (38): 1222-1223
• RF LDMOS characterization and its compact modeling 2001 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3 Jang, J. J., Tornblad, O., Arnborg, T., Chen, Q., Banerjee, K., Yu, Z. P., DUTTON, R. W. 2001: 967-970

  View details for Web of Science ID 000175125500225

• Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices Pop, E., Banerjee, K., Sverdrup, P., Dutton, R., W., Goodson, K. 2001
• High Frequency Characterization and Modeling of VLSI On-Chip Interconnects Qi, X., Kleveland, B., Wang, G., Yu, Z., Wong, S., S., Dutton, R., W. 2001
• A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance Lu, Y., Banerjee, K., Celik, M., Dutton, R., W. 2001
• Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design Oh, K-H., Duvvury, C., Salling, C., Banerjee, K., Dutton, R., W. 2001
• Quantum Transport Model for sub-100nm CMOS Devices Yu, Z., Yergeau, D., W., Dutton, R., W., Svizhenko, A., Anantram, M., P. 2001
• Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications Ito, C., Banerjee, K., Dutton, R., W. 2001
• Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection Oh, K, H., Duvvury, C., Banerjee, K., Dutton, R., W. 2001
• Density Functional Theory Study of Hf and Zr Aluminates as High-k Gate Dielectrics Haverty, M., Kawamoto, A., Jun, G., Cho, K., Dutton, R., W. 2001
• Impact of Gate Tunneling Current in Scaled MOS on Circuit Performance: A Simulation Study Choi, C-H., Yu, Z., Dutton, R., W. 2001
• Design Methodology for Power-Constrained Low Noise RF Circuits Goo, J-S., Ahn, H, T., Ladwig, D., J., Yu, Z., Lee, T., H., Dutton, R., W. 2001
• Fast Placement-Dependent Full Chip Thermal Simulation Yu, Z., Yergeau, D., Dutton, R., W., Nakagawa, S., Deeney, J. 2001
• Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed Signal and RF Applications Ito, C., Banerjee, K., Dutton, R., W. 2001
• Impact of substrate resistance on drain current noise in MOSFETs SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2001 Goo, J. S., Donati, S., Choi, C. H., Yu, Z. P., Lee, T. H., DUTTON, R. W. 2001: 182-185

  View details for Web of Science ID 000172900500040

• Macroscopic quantum carrier transport modeling SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2001 Yu, Z. P., DUTTON, R. W., YERGEAU, D. W., Ancona, M. G. 2001: 1-9

  View details for Web of Science ID 000172900500001

• Large signal analysis of on-chip interconnects using transport based approach 2000 5TH INTERNATIONAL SYMPOSIUM ON ANTENNAS, PROPAGATION AND EM THEORY PROCEEDINGS Wang, G. F., Qi, X. N., Yu, Z. P., DUTTON, R. W., Rafferty, C. S. 2000: 309-312

  View details for Web of Science ID 000165985500079

• Qualification of Hemodynamics in the Human Abdominal Aorta using Level Set Based Vascular Modeling Wang, K., Dutton, R., W., Taylor, C. 2000
• Advanced Electro-Thermal Modeling and Simulation Techniques for Deep Sub-Micron Devices Sverdrup, P., G., Sinha, S., Pop, E., Tornblad, O., Dutton, R., W., Goodson, K., E. 2000
• Well-tempered MOSFETs: 1D Versus 2D Quantum Analysis Abramo, A., Selmi, L., Yu, Z., Dutton, R., W. 2000
• Atomic Scale Effects of Zirconium and Hafnium Incorporation at a Model Silicon/silicate Interface by First Principles Calculations Kawamoto, A., Jameson, J., Griffin, P., B., Cho, K., Dutton, R., W. 2000
• Internet Based Modeling of Micro-Electro-Mechanical Systems Wilson, X., M., Yergeau, D., W., Dutton, R., W. 2000
• Guidelines for the power constrained design of a CMOS tuned LNA 2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES Goo, J. S., Oh, K. H., Choi, C. H., Yu, Z. P., Lee, T. H., DUTTON, R. W. 2000: 269-272

  View details for Web of Science ID 000166421700067

• Sub-continuum thermal simulations of deep sub-micron devices under ESD conditions 2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES Sverdrup, P. G., Banerjee, K., Dai, C. H., Shih, W. K., DUTTON, R. W., Goodson, K. E. 2000: 54-57

  View details for Web of Science ID 000166421700013

• Shallow Source/Drain Extension Effects on External Resistance in Sub-0.1mm MOSFET's IEEE Trans. Elect. Dev. Choi, C, H., Goo, J, S., Yu, Z., Dutton, R., W. 2000; 3 (47): 655-658
• Effect of Surface Properties on the Effective Electrical Gap of Electrostatically Actuated Micromechanical Devices MSM Chan, E., K., Dutton, R., W. 2000
• Modeling and simulation of phonon boundary scattering in PDE-based device simulators 2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES Tornblad, O., Sverdrup, P. G., Yergeau, D., Yu, Z., Goodson, K. E., DUTTON, R. W. 2000: 58-61

  View details for Web of Science ID 000166421700014

• Issues in high frequency noise simulation for deep submicron MOSFETs UNSOLVED PROBLEMS OF NOISE AND FLUCTUATIONS Goo, J. S., Choi, C. H., Danneville, F., Yu, Z. P., Lee, T. H., DUTTON, R. W. 2000; 511: 401-406

  View details for Web of Science ID 000086805200045

• Equivalence of van der Ziel and BSIM4 Models in Modeling the Induced Gate Noise of MOSFETs Goo, J, S., Liu, W., Choi, C, H., Green, K., R., Yu, Z., Lee, T., H., Dutton, R. W. 2000
• GEODESIC: A New and Extensible Geometry Tool and Framework with Application to MEMS Wilson, N., M., Wang, K., Yergeau, D., W., Dutton, R., W. 2000
• Compact Electrothermal Modeling of RF Power LDMOS Tornblad, O., Jang, J., Qi, X., Arnborg, T., Chen, Q., Yu, Z., Dutton, R. W. 2000
• CMOS and Possible “Replacements” for 2010 Dutton, R., W. 2000
• On-chip Inductance Modeling and RLC Extraction of VLSI Interconnects for Circuit Simulations Qi, X., Wang, G., Yu, Z., Dutton, R., W., Young, T., Chang, N. 2000
• Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices Zhang, X., Y., Banerjee, K., Amerasekera, A., Gupta, V., Yu, Z., Dutton, R., W. 2000
• Full Chip Thermal Simulation Yu, Z., Yergeau, D., W., Dutton, R., W. 2000
• On-chip Inductance Modeling of VLSI Interconnects Qi, X., Kleveland, B. 2000
• Fast Wavelet Multigrid Algorithm for Solution of Electromagnetic Integral Equations Microwave and Optical Technology Letters Wang, G., Dutton, R., W., Hou, J. 2000; 2 (24): 86-91
• Modelling, Calibration and Validation of Contributions to Stress in the Shallow Trench Isolation Process Sequence Garikipati, K., Rao, V., S., Hao, M., Y., Ibok, E., de Wolf, I., Dutton, R., W. 1999
• A Bias Dependent Source/Drain Resistance Model in LDD MOSFET Devices for Distortion Analysis Oh, K, H., Yu, Z., Dutton, R., W. 1999
• Modeling of MOS Scaling with Emphasis on Gate Tunneling and Source/Drain External Resistance Third NASA Workshop on Device Modeling Dutton, R., W., Choi, C, H. 1999
• A Novel Method to Utilize Existing TCAD Tools to Build Accurate Geometry Required for MEMS Simulation MSM, San Juan, Puerto Rico Wilson, N., M., Liang, S., Pinsky, P., M., Dutton, R., W. 1999
• Integration of TCAD Tools into CAD Tools for MEMS Wilson, N., M., Pinsky, P., M., Dutton, R., W. 1999
• Line Inductance Extraction and Modeling in a Real Chip with Power Grid Kleveland, B., Qi, X., Madden, L., Dutton, R., W., Wong, S., S. 1999
• Investigation of Tetrahedral Automatic Mesh Generation for Finite-Element Simulation of Micro-Electro-Mechanical Switches Wilson, N., M., Pinsky, P., M., Dutton, R., W. 1999
• Complete Characterization of Electrostatically-Actuated Beams Including Effects of Multiple Discontinuities and Buckling Chan, E., K., Garikipati, K., Dutton, R., W. 1999
• A Quasi-Mixed-Mode MOSFET Model for Simulation and Prediction of Substrate Resistance under ESD Stress and Layout Variations Zhang, X., Y., Yu, Z., Dutton, R., W. 1999
• Density-Gradient Analysis of Tunneling in MOS Structures with Ultra-Thin Oxides Ancona, M., G., Yu, Z., Dutton, R., W., Voorde, P., V., Cao, M., Vook, D. 1999
• Circuit Model for Power LDMOS Including Quasi-Saturation Jang, J., Arnborg, T. 1999
• Level Sets for Vascular Model Construction in Computational Hemodynamics Wang, K., C., Parker, D., Dutton, R., W., Taylor, C., A. 1999
• Effects of Capacitors, Resistors and Residual Charge on the static and Dynamic Performance of Electrostatically-Actuated Devices Chan, E., K., Dutton, R., W. 1999
• TCAD--Yesterday, Today and Tomorrow,” Invited Paper, Special Issue on TCAD for Semiconductor Industries IEICE Trans. Electron Dutton, R., W. 1999; 6 (E82-C): 791-799
• Direct Tunneling Current Model for Circuit Simulation IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Choi, C, H., Oh, K., H., Goo, J., S., Yu, Z., Dutton, R., W. 1999: 735-738
• Analysis of Distortion Behavior Considering Polydepletion Effect in MOS Transistors SSDM '99, Tokyo, Japan Oh, K, H., Yu, Z., Dutton, R., W. 1999
• Issues in High Frequency Noise Simulation for Deep Submicron MOSFETs Goo, J, S., Choi, C, H., Danneville, F., Yu, Z., Lee, T., H., Dutton, R., W. 1999
• C-V and Gate Tunneling Current Characterization of Ultra-Thin Gate Oxide MOS (tox+1.3-1.8nm) Choi, C, H., Goo, J, S., Oh, T., Y., Yu, Z., Dutton, R., W., Bayoumi, A. 1999
• RF Noise Simulation for Submicron MOSFET's Based on Hydrodynamic Model Goo, J-S., Choi, C., Morifuji, E., Momose, H., S., Yu, Z., Iwai, H., Dutton, R. W. 1999
• Utilizing Existing TCAD Simulation Tools to Create Solid Models for the Simulation Based Design of MEMS Devices Wilson, N., M., Dutton, R., W., Pinsky, P., M. 1998
• Modeling and Simulation of an RF LDMOS Device Using Harmonic Balance PISCES Rotella, F., M., Ma, G., Yu, Z., Dutton, R., W. 1998
• Characterization of Electrostatically-Actuated Beams Through Capacitance-Voltage Measurements and Simulations Chan, E., K., Garikipati, K., Hsiau, Z., K., Dutton, R., W. 1998
• A Heterogeneous Environment for Computational Prototyping and Simulation Based Design of MEMS Devices Wilson, N., M., Hsiau, Z., K., Dutton, R., W., Pinsky, P., M. 1998
• Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer Choi, C., Yu, Z., Dutton, R., W. 1998
• Layout-based 3D Solid Modeling of IC Structures and Interconnects including Electrical Parameter Extraction Qi, X., Shen, S., Hsiau, Z., K, Yu, Z., Dutton, R., W. 1998
• Substrate Resistance Model for Simulating MOSFET Breakdown in ESD Protection TECHCON '98, Las Vegas, NV Zhang, X., Y., Yu, Z., Beebe, S., Dutton, R., W. 1998
• A fast 3D modeling approach to parasitics extraction of bonding wires for RF circuits INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST Qi, X. N., Yue, C. P., Arnborg, T., Soh, H. T., Yu, Z. P., DUTTON, R. W., Sakai, H. 1998: 299-302

  View details for Web of Science ID 000078581800069

• Hierarchical Process Simulation for Nano-Electronics Dutton, R., W., Kan, E., C. 1998
• Challenges in Process Modeling for MEMS Dutton, R., W., Chan, E., K., Hsiau, Z., K., Shen, S. 1998
• Level Set Methods and MR Image Segmentation for Geometric Modeling in Computational Hemodynamics Wang, K., C., Taylor, C., A., Hsiau, Z., Parker, D., Dutton, R., W. 1998
• A Common Mesh Implementation for Both Static and Moving Boundary Process Simulations Chen, T., Yergeau, D., W., Dutton, R., W. 1998
• Design Optimization of RF Power MOSFET's Using Large Signal Analysis Device Simulation of Matching Networks Rotella, F., Ma, G., Yu, Z., Dutton, R., W. 1998
• Multi-dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-level Programming Techniques Rafferty, C., S., Biegel, B., Yu, Z., Ancona, M., G., Bude, J., Dutton, R., W. 1998
• Improved performance and thermal stability of interdigitated power RF bipolar transistors with nonlinear base ballasting PROCEEDINGS OF THE 1997 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING Jang, J., Kan, E. C., DUTTON, R. W., Arnborg, T. 1997: 143-146

  View details for Web of Science ID 000071093100030

• Efficient Multi-tone Harmonic Balance Simulation of Semiconductor Devices in the Presence of Linear High-Q Circuitry Troyanovsky, B., Rotella, F., Yu, Z., Dutton, R., W., Arnborg, T. 1997
• Device Modeling and Simulation for VLSI Design Dutton, R., W. 1997
• A Computationally Stable Quasi-Empirical Compact Model for the Simulation of MOS Breakdown in ESD-Protection Circuit Design Lim, S., L., Zhang, X., Y., Yu, Z., Beebe, S., Dutton, R., W. 1997
• Next-Generation TCAD Tools--Supporting Rapid Prototyping of New Models and Numerics 1997 NASA Device Modeling Workshop Dutton, R., W., Kan, E., C., Yergeau, D., W., Yu, Z., Yu, Rafferty, C., S. 1997
• Gridding techniques for the level set method in semiconductor process and device simulation Kan, E. C., Hsiau, Z. K., Rao, V. N., DUTTON, R. W. I E E E. 1997: 327-330

  View details for Web of Science ID A1997BJ53T00082

• A new numerical formulation for thermal oxidation Rao, V. S., Hughes, T. J., Kan, E., DUTTON, R. W. I E E E. 1997: 237-240

  View details for Web of Science ID A1997BJ53T00059

• Device Modeling Challenges into the Next Century Dutton, R., W. 1997
• Harmonic Balance Device Analysis of an LDMOS RF Power Amplifier with Parasitics and Matching Network Rotella, F., M., Yu, Z., Dutton, R., W., Troyanovsky, B., Ma, G. 1997
• Nonlinear Dynamic Modeling of Micromachined Microwave Switches Chan, E., K., Kan, E., C., Dutton, R., W., Pinsky, P., M. 1997
• Density-Gradient Simulations of Quantum Effects in Ultra-Thin-Oxide MOS Structures Ancona, M., G., Yu, Z., Lee, W-C., Dutton, R., W., Voorde, P., V. 1997
• Mixed-Technology CAD for Integrated Systems--a Confluence of Electrical and Mechanical Perspectives Dutton, R., W., Kan, E., C. 1997
• Device Simulation for RF Applications IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Dutton, R., W., Troyanovsky, B., Yu, Z., Arnborg, T., Rotella, F., Ma, G. 1997: 301-304
• Stabilized Element Residual Method (SERM): A posteriori error estimation for the advection-diffusion equation JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS Agarwal, A. N., PINSKY, P. M. 1996; 74 (1-2): 3-17

  View details for Web of Science ID A1996VT30900002

• Advanced Geometric Techniques in 3D Process Simulation Golias, N., A., Dutton, R., W. 1996
• Circuit Embedded Device Simulation for Heterogeneous Circuitry Rotella, F., Yu, Z., Dutton, R., W. 1996
• Challenges in Computational Prototyping of Deep Sub-Micron Integrated Circuit Technology Dutton, R., W. 1996
• A New Practical Method to Include Recombination-Generation Process in Self-Consistent Monte Carlo Device Simulation Jin, G., Kan, E., C., Dutton, R., W. 1996
• The TCAD Road Ahead Dutton, R., W. 1996
• Efficient 3D Mesh Adaptation in Diffusion Simulation Chen, T., Yergeau, D., W., Dutton, R., W. 1996
• Parasitic characterization of radio-frequency (RF) circuits using mixed-mode simulation Jang, J. J., Kan, E. C., So, L., DUTTON, R. W. IEEE. 1996: 445-448

  View details for Web of Science ID A1996BF78V00097

• Parallel Adaptive Finite Element Software for Semiconductor Device Simulation Dutton, R., W., Law, K., H., Pinsky, P., M., Aluru, N., R., Herndon, B., P. 1996
• Accurate Doping Profile Determination Using TED/QM Models Extensible to Sub-quarter Micron nMOSFETs Voorde, P., V., Griffin, P., B., Yu, Z., Oh, S. Y., Dutton, R., W. 1996
• TCAD for Analog Circuit Applications: Virtual Devices and Instruments Dutton, R., W., Troyanovsky, B., Yu, Z., Kan, E., C., Wang, K., Chen, T. 1996
• Large Signal Analysis of RF/Microwave Devices with Parasitics Using Harmonic Balance Device Simulation Troyanovsky, B., Rotella, F., Yu, Z., Dutton, R., W., Sato-Iwanaga, J. 1996
• ESD Simulation to Find Correlation Between Junction Depth and Snapback Slope Using 0.35mm LDD MOSFETS Zhang, X., Y., Yu, Z., Dutton, R., W., Beebe, S. 1996
• Atomic-Scale and Hierarchical Modeling for Nano-Electronics Dutton, R., W., Kan, E., C. 1996
• Accurate C-V Characterization of Quarter-Micron MOS Devices Using Quantum Mechanical Corrections and AC Simulations Yu, Z., Griffin, P., B., Dutton, R., W. 1996
• 2D/3D Etching and Deposition Simulation Tools Implemented with a General TCAD Geometry Server Hsiau, Z-K., Kan, E., C., McVittie, J., P., Dutton, R., W. 1996
• 3D Solid Modeling of IC Structures Using Simulated Surface Topography Wang, K., Park, H., Yu, Z., Kan, E., C., Dutton, R., W. 1996
• Modeling and Characterization of Three-Dimensional Effects in Physical Etching and Deposition Simulation Hsiau, Z-K., Kan, E., C., Bang, D., S., McVittie, J., P., Dutton, R., W. 1996
• Distortion Analysis of GaAs MESFETs Based on Physical Model using PISCES-HB IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Sato-Iwanaga, J., Fujimoto, K., Masato, H., Ota, Y., Inoue, K., Troyanovsky, B., Dutton, R. W. 1996: 163-166
• A TCAD Based Golden Standard for MOS Technology Scaling and Compact Model Development Mujtaba, S., A., Kan, E., C., Pinto, M., R., Rafferty, C., S., Yu, Z., Dutton, R., W. 1996
• Physical Etching/Deposition Simulation with Collision-Free Boundary Movement IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Hsiau, Z, K., Kan, E., C., McVittie, J., P., Dutton, R., W. 1995: 101-104
• Unification of Macroscopic Impact Ionization Models for Nonhomogeneous Fields Kan, E., C., Dutton, R., W. 1995
• An Accurate NMOS Mobility Model for 0.25mm MOSFETs Mujtaba, S., A., Pinto, M., R., Boulin, D., M., Rafferty, C., S., Dutton, R., W. 1995
• ALAMODE: A Layered Architecture for Model Development Yergeau, D., W., Kan, E., C., Gander, M., J., Dutton, R., W. 1995
• Physical Modeling of Surface and Heterojunction for Mesa-Structured HBTs Kan, E., C., Dutton, R., W. 1995
• Advance in Numerical Methods for Convective Hydrodynamic Model of Semiconductor Devices Aluru, N., R., Law, K., H., Dutton, R., W. 1995
• Accurate Modeling of Coulombic Scattering, and its Impact on Scaled MOSFETs Mujtaba, S., A., Takagi, S., I., Dutton, R., W. 1995
• Layout-based 3D Solid Modeling for IC Yu, Z., Wang, K., Chen, T., Dutton, R., W., Watt, J., T. 1995
• FIESTA-HD: A Parallel Finite Element Program for Hydrodynamic Device Simulation Parallel CFD '95, California Inst. of Technology, Pasadena, CA Aluru, N., R., Law, K., H., Raefsky, A., Dutton, R., W. 1995
• Quasi-Three-Dimensional Modeling of Sub-Micron LOCOS Structures IEEE Trans on Semiconductor Manufacturing Park, H., Smeys, P., Sahul, Z., H., Saraswat, K., C., Dutton, R., W., Hwang, H. 1995; 4 (8): 390-401
• Numerical Solution of Two-carrier Hydrodynamic Semiconductor Device Equations Employing a Stabilized Finite Element Method Comput. Methods in Appli. Mech. Eng. Aluru, N., R., Law, K., H., Raefsky, A., Pinsky, P., M., Goossens, R., J. G., Dutton, R., W. 1995; 125: 187-220
• A Vector Level Control Function for Generalized Octree Mesh Generation SISDEP '95 Chen, T., Johnson, J., Dutton, R., W. 1995
• Virtual Instruments for Development of High Performance Circuit Technologies Dutton, R., W., Yu, Z., Rotella, F., Beebe, S., Troyanovsky, B., So, L. 1995
• Hierarchical Process Simulation for Nano-Electronics Dutton, R., W., Kan, E., C., Onga, S., Okada, T. 1995
• Device/Circuit Simulation for Heterogeneous Technology Yu, Z., Rotella, F., Troyanovsky, B., Dutton, R., W. 1995
• Dynamic Trapping Model for Analysis of GaAs MESFETs and Quantum Well Lasers Yu, Z., Dutton, R., W., Harrison, W., A., Liu, Y. 1995
• Hot Electron Transistors on Silicon Substrate (HESS)-A Computational Prototyping Kan, E., C., Jin, G., Y., Dutton, R., W. 1995
• Parallelizing a PDE Solver: Experiences with PISCES-MP Herndon, B., P., Raefsky, A., Dutton, R., W. 1995
• Formulation of a Tail Electron Hydrodynamic Model Based on Monte Carlo Results IEEE Electron Dev. Lett. Yao, C. S., Ahn, J. G., Park, Y. J., Min, H. S., Dutton, R., W. 1995; 1 (16): 26-29
• A Methodology for Parallelizing PDE Solvers: Applications to Semiconductor Device Simulation Herndon, B., P., Aluru, N., R., Raefsky, A., Goossens, R., J. G., Law, K., H., Dutton, R., W. 1995
• Large Signal Frequency Domain Device Analysis Via the Harmonic Balance Technique Troyanovsky, B., Yu, Z., Dutton, R., W. 1995
• Simulation of Deep Submicron SOI N-MOSFET Considering the Velocity Overshoot Effect IEEE Electron Dev. Lett Choi, W, S., Assaderaghi, F., Park, Y. J., Min, H, S., Hu, C., Dutton, R., W. 1995; 7 (16): 333-335
• Relaxation-Based Harmonic Balance Technique for Semiconductor Device Simulation ICCAD '95, San Jose, CA Troyanovsky, B., Yu, Z., So, L., Dutton, R., W. 1995: 700-703
• Comment on ‘Experimental Investigation and Modeling of the Role of Extended Defects during Thermal Oxidation’ [J. Appl. Phys. 74, 5821 (1993)] J. Appl. Phys. Huang, R., Y. S., Dutton, R., W. 1994; 10 (76): 6020-6021
• Layout-based Extraction of IC Electrical Behavior Model Wang, K., Rotella, F., Chen, T., Yang, D., Lee, A., Yu, Z., Dutton, R. W. 1994
• An Alternative Method for Compact Model Construction and Parameter Extraction Kan, E., C., Dutton, R., W. 1994
• An Integrated Simulation Environment for Electronic Packages Lee, A., Dutton, R., W., Yu, Z., Wang, K. 1994
• Parasitic Extraction Based on SWR3D Framework Lee, A., Dutton, R., W. 1994
• Next-Generation Stanford TCAD-PISCES 2ET and SUPREM 007 IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Beebe, S., Rotella, F., Sahul, Z., H., Yergeau, D., W., McKenna, G., So, L., Dutton, R. W. 1994: 213-216
• Dual Energy Transport Model for Advanced Device Simulations Yu, Z., So, L., Kan, E., C., Dutton, R., W. 1994
• Integrated TCAD for OEIC Applications Invited paper, OE/LASE '94, SPIE Workshop, Los Angeles, CA Dutton, R., W. 1994
• A Comparison of Numerical Solutions of the Boltzmann Transport Equation for High-Energy Electron Transport Silicon IEEE Trans. Electron Devices Abramo, A., Baudry, L., Brunetti, R., Castagne, R., Charef, M., Dessenne, F., Dutton, R. W. 1994; 9 (41): 1646-1654
• Accurate Modeling of GaAs MESFET Sidegating Effects by Trapping Simulation Liu, Y., Yu, Z., Dutton, R., W., Deal, M., D. 1994
• Simulation of Tungsten Etchback for Via and Contact Plugs Hsiau, K., Bang, D., S., McVittie, J., P., Dutton, R., W., Saraswat, K., C., Tripathi, S. 1994
• Technology CAD: Computer Simulation NTU Short Course Dutton, R., W. 1994
• An Automatic Biasing Scheme for Tracing Arbitrarily Shaped I-V Curves IEEE Trans. on Computer-Aided Design Goossens, R., J. G., Beebe, S., Yu, Z., Dutton, R., W. 1994; 3 (13): 310-317
• Impact Ionization Modeling Using Simulation of High Energy Tail Distributions Ahn, J., Yao, C. S., Park, Y. J., Min, H. S., Dutton, R., W. 1994
• Grid Evolution for Oxidation Simulation using a Quadtree Based Grid Generator Sahul, Z., H., McKenna, E., W., Dutton, R., W. 1994
• A Self-Consistent Approach to Substrate Current Simulation in Submicron MOSFETs So, L., L., Kan, E., C., Yu, Z., Dutton, R., W. 1994
• A General OO-PDE Solver for TCAD Applications Yergeau, D., W., Dutton, R., W., Goossens, R., J. G. 1994
• Further Improvements in Decoupled Methods for Semiconductor Device Modeling Obrecht, M., S., Heasell, E., L., Elmasry, M., I., Wu, K-C., Dutton, R., W. 1994
• Space-Time Galerkin/Least Squares Finite-Element Formulation for the Hydrodynamic Device Equations IEICE Trans. Elect. Aluru, N., R., Law, K., H., Pinsky, P., M., Raefsky, A., Goossens, R., J. G., Dutton, R., W. 1994; 2 (E77-C): 227-236
• Semi-Empirical Local NMOS Mobility Model for 2-D Device Simulation Incorporating Screened Minority Impurity Scattering NUPAD V Conference, Honolulu, HI Mujtaba, S., A., Dutton, R., W., Scharfetter, D., L. 1994: 3-6
• PISCES-2ET--Two Dimensional Device Simulation for Silicon and Heterostructures Stanford University Yu, Z., Chen, D. 1994
• Formulation of Macroscopic Transport Model for Numerical Simulation of Semiconductor Devices Invited Paper, VLSI Design Kan, E., C., Chen, D., Ravaioli, U., Yu, Z., Dutton, R., W. 1994; 2 (3): 211-224
• Algorithms and TCAD Software Using Parallel Computation Invited Paper, 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan Dutton, R., W. 1993: 10-12
• The Effect of Amorphizing Implants on Boron Diffusion Huang, R., Y. S., Dutton, R., W. 1993
• Dual Energy Transport Model for Coupled Lattice and Carrier Systems So, L., Chen, D., Yu, Z., Dutton, R., W. 1993
• Virtual Instruments--Concept and Implementation Yu, Z., Dutton, R., W. 1993
• Grid and Geometry Techniques for Multi-Layer Process Simulation Sahul, Z., H., Dutton, R., W., Noell, M. 1993
• Improvement of Initial Solution Projection in Solving General Semiconductor Equations Including Energy Transport So, L., Chen, D., Yu, Z., Dutton, R., W. 1993
• Technology CAD at Stanford University: Physics, Algorithms, Software, and Applications Dutton, R., W., Goossens, R., J.G. edited by Fasching, F., Halama, S., Selberherr, S. Microelectronics Journal. 1993, 1995
• Solid Modeling-Based Parametric Operations for Device Design 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan Wong, W., T., Yang, D., X., Dutton, R., W., Plummer, J., D. 1993: 136-137
• Space-time Galerkin/Least Squares Finite-Element Formulation for the Hydrodynamic Device Equations 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan Aluru, N., R., Law, K., H., Pinksy, P., M., Raefsky, A., Goossens, R., J.G., Dutton, R., W. 1993: 16-17
• δ-Zone Triangulation: A Boundary Refinement Scheme for Quadtree Based Mesh Yang, D., Dutton, R., W., Law, K., H. 1993
• Technology CAD at Stanford University: Physics, Algorithms, Software, and Applications Invited Paper, SISDEP '93, Vienna, Austria Dutton, R., W., Goossens, R., J. G. 1993
• A Finite Element Formulation for the Hydrodynamic Semiconductor Device Equations Computer Methods in Applied Mechanics and Engineering Aluru, N., R., Raefsky, A., Pinsky, P., M., Law, K., H., Goossens, R., J.G., Dutton, R., W. 1993; 107: 269-298
• The Effects of High-Dose Silicon Implants on Boron Diffusion Huang, R., Y. S., Dutton, R., W. 1993
• Grid Techniques for Multi-Layer Device and Process Simulation Sahul, Z., H., McKenna, E., Dutton, R., W. 1993
• Dual Energy Transport Model with Coupled Lattice and Carrier Temperatures Chen, D., Yu, Z., Goossens, R., Wu, K, C., Dutton, R., W. 1993
• Modeling of the Charge Balance Condition on Floating Gates and Simulation of EEPROM's IEEE Trans. on CAD Chen, D., S., Sugino, S., Yu, Z., Dutton, R., W. 1993; 10 (12): 1499-1502
• Modeling of IC Technology--A Challenge to both Physics and Computation Bulletin of the Japan Society for Industrial and Applied Mathematics Dutton, R., W. 1993; 3 (3): 16-28
• Experimental Investigation and Modeling of the Role of Extended Defects During Thermal Oxidation J. Appl. Phys. Huang, R., Y. S., Dutton, R., W. 1993; 9 (74): 5821-5827
• Technology CAD: Computer Simulation of IC Processes and Devices Dutton, R., W., Yu, Z. Kluwer Academic Publishers. 1993
• The Role of TCAD in Parasitic Analysis of ICs Invited Paper, ESSDERC '93, Grenoble, France Dutton, R., W. 1993: 75-81
• Robust Simulation of GaAs Devices Using Energy Transport Model 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan So, L., L., Chen, D. 1993: 32-33
• An Efficient Impact Ionization Model for Silicon Monte Carlo Simulation 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD) Digest, Nara, Japan Yao, C., - S., Chen, D., Dutton, R., W., Venturi, F., Sangiorgi, E., Abramo, A. 1993: 42-43
• The Role of Extended Defects in Dopant Diffusion Huang, R., Y. S., Roth, D., J., Plummer, J., D., Dutton, R., W. 1993
• Silicon Interstitial Absorption During Thermal Oxidation at 900ºC by Extended Defects Formed Via Silicon Implantation Appl. Phys. Lett. Roth, D., J., Huang, R., Y.S., Plummer, J., D., Dutton, R., W. 1993; 20 (62): 2498-2500
• SCHOTTKY CONTACT EFFECTS IN THE SIDEGATING EFFECT OF GAAS DEVICES IEEE ELECTRON DEVICE LETTERS Yi, L., DUTTON, R. W., Deal, M. D. 1992; 13 (3): 149-151

  View details for Web of Science ID A1992HE79600005

• Power Semiconductor Devices and Circuits Tool Integration for Power Device Modeling Including 3D Aspects Dutton, R., W., Plummer, J., D. edited by Jaeklin, A., A. Plenum Press. 1992: 1
• PISCES-MP - Adaptation of a Dusty Deck for Multiprocessing Herndon, B., P., Raefsky, A., Goossens, R., J.G., Dutton, R., W. 1992
• A Finite Element Formulation for the Hydrodynamic Semiconductor Device Equations Aluru, N., R., Raefsky, A., Pinsky, P., M., Law, K., H., Goosens, J., G., Dutton, R., W. 1992
• Numerical Characterization of a New Energy Transport Model International Workshop on Computational Electronics, U. Illinois, Urbana-Champaign, IL Edwin, E., C., Chen, D., Ravaioli, U., Dutton, R., W. 1992
• Mega-Scale TCAD--Modeling Challenges for the 1990's Dutton, R., W. 1992
• Comments, with Reply, on ‘Shottky Contact Effects in the Sidegating Effect of GaAs Devices IEEE Electron Dev. Lett Ayyar, S., G., Liu, Y., Dutton, R., W., Deal, M., D. 1992; 10 (13): 547-548
• Analysis of Spurious Velocity Overshoot in Hydrodynamic Simulations NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, Seattle, WA Chen, D., Sangiorgi, E., Pinto, M., R., Kan, E., C., Ravaioli, U., Dutton, R., W. 1992: 109-114
• A Utility-based Integration System for Process Simulation IEEE Trans. CAD Scheckler, E., Wong, A., Wang, R., Chin, G., Dutton, R., W. 1992; 7 (11): 911-920
• A Tool Towards Integration of IC Process, Device, and Circuit Simulation IEEE J. Solid-State Circuits Chin, G., Dutton, R., W. 1992; 3 (27): 265-273
• Extraction of Charge Partitioning in Multi-terminal Devices with AC Analysis Approach Wu, K, C., So, L., Yu, Z., Dutton, R., W., Faricelli, J. 1992
• Device CAD in the '90's: At the Crossroads Goossens, R., J.G., Dutton, R., W. 1992
• Robust and Efficient AC Analysis of High-speed Devices IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Wu, K, C., Yu, Z., So, L., Dutton, R., W., Sato-Iwanaga, J. 1992: 935-938
• Analysis of Writing and Erasing Procedures of Flotox EEPROM Using the New Charge Balance Condition (CBC) Model NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, Seattle, WA Sugino, S., Chen, D., Takakura, N., Dutton, R., W. 1992: 65-69
• An Automated Mesh Refinement Scheme Based on Level-Control Function NUPAD IV (Numerical Process and Device Modeling Workshop) Digest, Seattle, WA Yang, D., Law, K., H., Dutton, R., W. 1992: 181 - 186
• Comparison between Hydrodynamic and Monte Carlo Models for Silicon Device Simulation Sangiorgi, E., Chen, D., Pinto, M., R., Dutton, R., W. 1992
• Numerical Techniques on Enhancing Robustness for Stress-Dependent Oxidation Simulation Using Finite Element Method in SUPREM-IV IEICE Trans. Elec. Oda, Y., Yu, K, S., Tung, T, L., Raefsky, A., Scharfetter, D., L., Dutton, R., W. 1992; 2 (E75-C): 150-155
• An Improved Energy Transport Model Including Nonparabolicity and Non-Maxwellian Distribution Effects IEEE Elec. Dev. Lett. Chen, D., Kan, E., C., Ravaioli, U., Shu, C, W., Dutton, R., W. 1992; 1 (13): 26-28
• An Approach to Construct Pre-Conditioning Matrices for Block Iteration of Linear Equations IEEE Trans. on CAD Wang, Z, Y., Wu, K, C., Dutton, R., W. 1992; 11 (11): 1334-1343
• A Modularized, Mixed IC Device/Circuit Simulation System Yu, Z., Wang, H., Dutton, R., W. 1992
• Linking TCAD to EDA - Benefits and Issues Chin, G., Dietrich, W., C., Boning, D., S., Wong, A., S., Neureuther, A., R., Dutton, R., W. 1991
• Accurate Modeling and Numerical Techniques in Simulation of Impact-ionization Effects on BJT Characteristics Yu, Z., Chen, D., Goossens, R., J. G., Dutton, R., W., Voorde, P., V., Oh, S., Y. 1991
• Picosecond Optoelectronic Gating of Silicon Bipolar Transistors by Locally Integrated GaAs Photoconductive Devices IEEE Electron Dev. Lett Morse, J., D., Mariella, Jr., R. P, Anderson, G., D., Dutton, R., W. 1991; 7 (12): 379-381
• A Tool Towards Integration of IC Process, Device, and Circuit Simulation Chin, G., Yu, Z., Dutton, R., W. 1991
• On-chip Picosecond Time-Domain Measurement of Silicon Bipolar Transistor Characteristics Using Integrated GaAs Photoconductive Devices Anderson, G., D., Dutton, R., W., Morse, J., D., Mariella Jr., R., P. 1991
• Parallelization of Monte Carlo Simulation for Submicron MOSFET on Hypercube Multiprocessors Yao, C., S., Sugino, S., Dutton, R., W. 1991
• Parallelization of Monte Carlo Analysis on Hypercube Multiprocessors and on a Networked EWS System Sugino, S., Yao, C., S., Dutton, R., W. 1991
• 1 GHz Integrated Poly-Si and -SiGe Photoconductors with BiCMOS Compatibility Hai, A., Morse, J., D., Dutton, R., W. 1991
• Technology Limitations for N+/P+ Polycide Gate CMOS due to Lateral Dopant Diffusion in Silicon/Polysilicon Layers IEEE Elect. Dev. Lett. Chu, C., L., Chin, G., Saraswat, K., C., Wong, S., S., Dutton, R., W. 1991; 12 (12): 696-698
• Process Simulators for Silicon VLSI and High Speed GaAs Devices Integrated Circuits Laboratory Plummer, J., D., Dutton et. al, R., W. 1991
• Numerical Small-Signal AC Modeling of Deep-Level-Trap Related Frequency-Dependent Output Conductance and Capacitance for GaAs MESFET's on Semi-insulating Substrates IEEE Trans. Elect. Dev. Li, Q., Dutton, R., W. 1991; 6 (38): 1285-1289
• Modeling Capture, Emission and Impact Ionization of Deep-Level Traps for GaAs Semi-Insulating Substrates IEEE Trans. on Elect. Dev. Li, Q., Dutton, R., W. 1991; 4 (38): 936-939
• Analytical Model and Numerical Simulation of High-level Injection in Si/SiGe HBTs Yu, Z., Dutton, R., W., Voorde, P., V., Oh, S., Y., Cottrell, P., E. 1991
• A STRIDE Towards Practical 3-D Device Simulation--Numerical and Visualization Considerations IEEE Trans. CAD Wu, K, C., Chin, G., R., Dutton, R., W. 1991; 9 (10): 1132-1140
• A Self-consistent Discretization Scheme for Current and Energy Transport Equations SISDEP '91 Digest, Zurich Chen, D., Kan, E., C., Ravaioli, U., Yu, Z., Dutton, R., W. 1991; 4: 235-240
• Modeling of Submicron Dry Etching Technology Using SUPREM-IV and SPEEDIE Uhm, K., S., Chin, G., Dutton, R., W., McVittie, J., P., Saraswat, K., C. 1990
• A Utility-Based Integrated Process Simulation System Scheckler, E., W., Wong, A., S., Wang, R., H., Chin, G., Camagna, J., R., Toh, K., K. H., Dutton, R. W. 1990
• Process and Device Simulation for Metal-Oxide-Semiconductor/Very Large Scale Integration Circuits Soviet Physics-Semiconductors Antognetti, P., Antoniadis, D., A., Dutton, R., W., Oldham, W., G. 1990; 5 (24): 599
• Modeling of Hot Carrier Effects for 0.5 Micron MOSFET's IEEE Trans. CAD/ICAS Hwang, C., G., Yabuta, A., Dutton, R., W. 1990
• Numerical Analysis of Breakdown Voltage Using Quasi Three Dimensional Device Simulation IEEE Trans. Electron Devices Yabuta, A., Hwang, C., G., Suzumura, M., Dutton, R., W. 1990; 4 (37): 1132-1140
• Annual Research Summary, Process and Device Modeling Principal Investigator Dutton, R., W. 1990
• Etching, Deposition, Diffusion, and Oxidation Models in SUPREM-IV Huang, R., Y. S., Aum, P., Griffin, P., B., Plummer, J., D., Dutton, R., W. 1990
• Modeling and Simulation of High-Level Injection Behavior in Double Heterojunction Bipolar Transistors Yu, Z., Cottrell, P., E., Dutton, R., W. 1990
• Intelligent Simulation for Optimization of Fabrication Processes Wenstrand, J., S., Iwai, H., Norishima, M., Tanimoto, H., Wada, T., Dutton, R., W. 1990
• Algorithms for `Curve-Tracer' Mode in Simulation of Devices with Highly Nonlinear Characteristics Dutton, R., W., Yu, Z. 1990
• A STRIDE Toward Practical 3D Device Simulation--Computational and Visualization Considerations Chin, G., Wu, K., C., Dutton, R., W. 1990
• Sidegating Effect of GaAs MESFETs and Leakage Current in a Semi-Insulating GaAs Substrate IEEE Electron Dev. Lett. Liu, Y., Dutton, R., W., Deal, M., D. 1990; 11 (11): 505-507
• Modeling of Bias-Stress Dependent Transconductance Degradation of Submicron MOSFETs IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Sugino, S., Yu, Z., Venturi, F., Dutton, R., W. 1990: 459-462
• A Nonequilibrium One-Dimensional Quantum-Mechanical Simulation for AlGaAs/GaAs HEMT Structures IEEE Trans. Computer-Aided Design Takano, C., Yu, Z., Dutton, R., W. 1990; 11 (9): 1217-1224
• Metamorphosis of PISCES - Application-oriented Transformation of 2D Device Simulation Digest of Papers, SRC TECHCON '90, San Jose, CA Anderson, G., Chin, G., Eldredge, M., Raefsky, A., Yu, Z., Dutton, R., W. 1990: 331-334
• Defensive Programming' in the Rapid Development of a Parallel Scientific Program IEEE Trans. on CAD Cheng, D., Y., Deutsch, J., T., Dutton, R., W. 1990; 6 (9): 665-669
• TWO-DIMENSIONAL TRANSIENT ANALYSIS OF A COLLECTOR-UP ECL INVERTER IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS KUO, J. B., Yang, T. S., DUTTON, R. W., Wooley, B. A. 1989; 8 (10): 1038-1045

  View details for Web of Science ID A1989AP29100002

• TWO-DIMENSIONAL ANALYSIS OF A MERGED BIPMOS DEVICE IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS KUO, J. B., ROSSEEL, G. P., DUTTON, R. W. 1989; 8 (8): 929-932

  View details for Web of Science ID A1989AF59700012

• Scaling Rules for Bipolar Transistors in BiCMOS Circuits IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Rosseel, G., P., Dutton, R., W. 1989: 795-798
• A Manufacturing-Oriented Environment for Synthesis of Fabrication Processes Wenstrand, J., S., Iwai, H., Dutton, R., W. 1989
• Metastability of CMOS Latch /Flip-flop Kim, L-S., Cline, R., Dutton, R., W. 1989
• Improved Physical Modeling of Submicron MOSFET's Based on Parameter Extraction Using 2-D Simulation IEEE Trans. CAD/ICAS Hwang, C., G., Dutton, R., W. 1989; 4 (8): 370-379
• Application of Matrix Transformation Methods in Three-Dimensional Device Simulation Wu, K-C., Wang, Z-Y., Lucas, R., F., Dutton, R., W. 1989
• Turn-on Transient Analysis of a BiPMOS Device Kuo, J., B., Rosseel, G., P., Dutton, R., W. 1989
• Substrate Current Model for Submicrometer MOSFET's Based on Mean Free Path Analysis IEEE Trans. Elect. Hwang, C., G., Dutton, R., W. 1989; 7 (36): 1348-1354
• Picosecond Photoconductivity Using a Graded Bandgap AlxGa1-xAs Active Detecting Layer IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Morse, J., D., Mariella, R., P., Dutton, R., W. 1989: 721-724
• New Approaches in a 3-D One-Carrier Device Solver IEEE Trans. CAD/ICAS Wu, K, C., Lucas, R., F., Wang, Z., Y., Dutton, R., W. 1989; 5 (8): 528-537
• Modeling of the Distributed Gate RC Effects in MOSFET's IEEE Trans. CAD/ICAS Kim, L., S., Dutton, R., W. 1989; 12 (8): 1365-1367
• Improvement in Norm-Reducing Newton Methods for Circuit Simulation IEEE Trans. CAD/ICAS Yeager, H., R., Dutton, R., W. 1989; 5 (8): 538-546
• A Single-ended BiCMOS Sense Circuit for Digital Circuits Rosseel, G., P., Horowitz, M., A., Dutton, R., W., Cline, R., L. 1989
• Delay Analysis of BiCMOS Drivers Bipolar Circuits and Technology Meeting, Minneapolis, MN Rosseel, G., P., Dutton, R., W., Mayaram, K., Pederson, D., O. 1988: 220-222
• Parallel Electronic Circuit Simulation on iPSC System Yuan, C., P., Lucas, R., F., Chan, P., Dutton, R., W. 1988
• Methodology for Submicron Device Model Development IEEE Trans. on Computer-Aided Design Marash, V., Dutton, R., W. 1988; 2 (7): 299-306
• Verification of Analytic Point Defect Models Using SUPREM-IV IEEE Trans. on Computer-Aided Design Law, M., E., Dutton, R., W. 1988; 2 (7): 181-190
• Hot Carrier Analysis in Sub-0.1m GaAs MESFET Cheng, D., Y., Hwang, C., G., Allee, D., R., Pease, R., F. W., Dutton, R., W. 1988
• User Interfaces to Device and Process Simulation Tools TECHCON 88 Chin, G., Dutton, R., W. 1988
• The Effect of Implantation Damage on Arsenic/Phosphorus Codiffusion IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Law, M., E., Pfiester, J., R., Dutton, R., W. 1988: 640-643
• SUPREM-IV Users Manual Integrated Circuits Laboratory Law, M., E., Rafferty, C., S., Dutton, R., W. 1988
• Annual Research Summary Principal Investigator Dutton, R., W. 1988
• Quasi Steady State Approximation of Interstitial Diffusion during Oxidation of Silicon IEEE Trans. on Computer-Aided Design Law, M., E., Dutton, R., W. 1988; 2 (7)
• August 3, 1988 Research Summary Principal Investigators Dutton, R., W., Plummer, J., D., Saraswat, K., C. 1988
• The Efficient Simulation of Coupled Point Defect and Impurity Diffusion IEEE Trans. on Computer-Aided Design Kump, M., R., Dutton, R., W. 1988; 2 (7): 191-204
• New Approaches in a Parallel 3-D One-Carrier Device Solver NUPAD II, San Diego, CA Wu, K., C., Lucas, R., F., Wang, Z., Y., Dutton, R., W. 1988
• Bipolar Scaling for BiCMOS Circuits Rosseel, G., P., Dutton, R., W. 1988
• A New Impact Ionization Model for Submicron MOSFET's Hwang, C., G., Cham, K., Dutton, R., W. 1988
• Modeling of Hot Carrier Effects for 0.5 Micron MOSFET's Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, San Diego, CA Yabuta, A., Cheng, D., Y., Dutton, R., W. 1988
• Improvement in Norm-Reducing Newton Methods for Circuit Simulation NUPAD II, San Diego, CA Yeager, H., R., Dutton, R., W. 1988
• SUPREM 3.5 - Process Modeling of GaAs IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Deal, M., D., Hansen, S., E., Anholt, R., Chou, S., Plummer, J., D., Dutton, R., W. 1987: 256-259
• Future Bipolar Structure IEEE 1987 Bipolar Circuits and Technology Meeting Dutton, R., W., Kuo, J., B. 1987
• Two-Dimensional Transient Analysis of a Very Fast ECL Inverter Kuo, J., B., Dutton, R., W. 1987
• A Global Converge Technique for High Electron Mobility Transistor Circuits Yeager, H., R., Dutton, R., W. 1987
• A Parallel 3-D Poisson Solver on a Hypercube Multiprocessor Lucas, R., F., Wu, K., C., Dutton, R., W. 1987
• Users Guide to the Stanford HEMT SPICE Model Integrated Circuits Laboratory Yeager, H., R., Dutton, R., W. 1987
• Solid Phase Epitaxial Regrowth of Boron-Doped Polycrystalline Silicon Deposited by Low-Pressure Chemical Vapor Deposition Appl. Phys. Lett. Ghannam, M., Y., Dutton, R., W. 1987; 8 (51): 611-613
• Optimal Structure for Ballistic Electron of AlGaAs/GaAs Heterojunction Bipolar Transistor Hwang, C., G., Dutton, R., W. 1987
• Accurate Analysis of Impact Ionization Effects in Submicron MOSFET Devices Hwang, C., G., Dutton, R., W., Higman, J., M., Hess, K. 1987
• Avalanche Simulation Method Hwang, C., G., Dutton, R., W. 1987
• SUPREM Examples Stanford Electronics Laboratories Law, M., E., Rafferty, C., S., Dutton, R., W. 1987
• Two-Dimensional Process Modeling and SUPREM-IV Rafferty, C., S., Law, M., E., Dutton, R., W. 1986
• Kinetic Modeling and Measurement of Active Species Distribution During Dry Etching Uhm, K., S., Kump, M., R., McVittie, J., P., Dutton, R., W. 1986
• Modeling LOCOS Effects on Diffusion ECS Spring Meeting, Semiconductor Silicon 1986 Digest Rafferty, C., S., Law, M., E., Griffin, P., B., Shott, J., D., Dutton, R., W., Plummer, J., D. 1986: 426-436
• Monte Carlo Simulation of Schottky Diode Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits Hwang, C., G., Dutton, R., W. 1986
• Submicron 2D MOS Modeling ICCAD Marash, V., Dutton, R., W. 1986
• Study and Modeling of Boron Diffusion at Polysilicon-silicon Interfaces San Diego Electrochem. Soc. Mtg. Ghannam, M., Y., Plummer, J., D., Dutton, R., W. 1986
• The Use of Computer Aids in IC Technology Evolution Dutton, R., W., Pinto, M., R. 1986
• Modeling and Simulation for VLSI Dutton, R., W. 1986
• MOS Pass Transistors with Reduced Transient Error Charge Kuo, J., B., Fu, C, C., Dameron, D., H., Dutton, R., W., Wooley, B., A. 1986
• Quasi Steady State Approximation of Interstitial Diffusion During Oxidation of Silicon Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits Law, M., E., Dutton, R., W. 1986
• Modeling Corner Oxidation Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits Rafferty, C., S., Dutton, R., W. 1986
• Computer-Aided Design of Integrated Circuits Fabrication Processes for VLSI Devices Stanford Electronics Laboratories Plummer, J., D., Dutton et. al, R., W. 1986
• Dopant Diffusion under Conditions of Thermal Nitridation of Si and SiO2 P. M. Fahey, R. W. Dutton, in Semiconductor Silicon Fahey, P., M., Dutton, R., W. edited by Huff, H., R., Abe, T., Kolbesen, B. The Electrochemical Society, Inc.. 1986: 571
• SUPREM IV Users Manual Stanford Electronics Laboratories Law, M., E., Rafferty, C., S., Dutton, R., W. 1986
• New n-well Fabrication Techniques Based on 2D Process Simulation IEEE International Electron Devices Meeting (IEDM) Technical Digest, Los Angeles, CA Law, M., E., Rafferty, C., S., Dutton, R., W. 1986: 518-521
• Multi- Window Device Analysis of Hot Carrier Transport IEEE International Electron Devices Meeting (IEDM) Technical Digest, Los Angeles, CA Hwang, C., G., Cheng, D., Y., Yeager, H., R., Dutton, R., W. 1986: 563-566
• A Reply to Comments on Small Geometry MOS Transistor Capacitance Measurement Method Using Simple On-Chip Circuits IEEE Elect. Dev. Lett. Oristian, J., E., Iwai, H., Walker, J., T., Dutton, R., W. 1985; 1 (6): 64-67
• New Integrated Polysilicon Photoconductors for Ultrafast Measurements on Silicon IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Bowman, D., R., Dutton, R., W., Hammond, R., B. 1985: 117-120
• 2D Transient Simulation of IC Devices and Technology Dutton, R., W., Pinto, M., R. 1985
• Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology Joint Special Issue IEEE Trans. CAD/ICAS and IEEE Trans. Elec. Dev. Sangiorgi, E., Pinto, M., R., Swirhun, S., E., Dutton, R., W. 1985; 4,10 (4, 32)
• Low Field Channel Pinch-Off Mechanism in GaAs MESFET's Shenai, K., Dutton, R., W. 1985
• SEDAN III--A Generalized Electronic Material Device Analysis Program Stanford Electronics Laboratories Yu, Z., Dutton, R., W. 1985
• Computer-Aided Design of Integrated Circuits Fabrication Processes for VLSI Devices ICL 17-79, Stanford Electronics Laboratories, Technical Report No. ICL-17-79 Plummer, J., D., Dutton, R., W., Bravman, J., C., Deal, B., E., Helms, C., R., Saraswat, K., C. 1985
• Temperature Dependence of the Fermi Level Position at Al-nGaAs Interfaces Fabricated by Molecular Beam Epitaxy Shenai, K., Dutton, R., W., Eglash, S., J. 1985
• An Analytical Algorithm for Placement of Arbitrarily Sized Rectangular Blocks Lu, S., Dutton, R., W. 1985
• Velocity Saturation Effect on Short-Channel MOS Transistor Capacitance IEEE Electron Dev. Lett. Iwai, H., Pinto, M., R., Rafferty, C., S., Oristan, J., E., Dutton, R., W. 1985; 3 (6): 120-122
• PISCES II-B Supplementary Report Stanford Electronics Laboratories Pinto, M., R., Rafferty, C., S., Yeager, H., R., Dutton, R., W. 1985
• Data Requirements and Program Interfaces for Simulating Integrated-Circuit Technology Invited Paper, IEEE ElectroTechnology Review Dutton, R., W. 1984: 49-51
• High Performance Latchup Free CMOS Sangiorgi, E., Swirhun, S., Weeks, A., Pinto, M., Rafferty, C., Saraswat, K., Dutton, R. W. 1984
• Nonplanar Schottky Device Analysis and Applications Sangiorgi, E., Rafferty, C., S., Pinto, M., R., Dutton, R., W. 1984
• Latchup Free CMOS Using Guarded Schottky Barrier PMOS Swirhun, S., Sangiorgi, E., Weeks, A., Swanson, R., M., Saraswat, K., C., Dutton, R., W. 1984
• Electrical End Point Detection of Plasma Etched IC Contact Openings Chang, G., McVittie, J., P., Walker, J., T., Dutton, R., W. 1984
• Simulation of Multilayer Structures for VLSI Using the SUPREM-III Process Simulation Program Hansen, S., E., Shott, J., D., Fahey, P., M., Plummer, J., D., Dutton, R., W. edited by Board, K., Owen, D., R. J. 1984
• Small Geometry MOS Transistor Capacitance Measurement Method Using Simple On-Chip Circuits IEEE Electron Dev. Lett. Oristian, J., E., Iwai, H., Walker, J., T., Dutton, R., W. 1984; 10 (5): 395-397
• Modeling of Polysilicon Dopant Diffusion for Shallow-Junction Bipolar Technology IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Barbuscia, G., P., Chin, G., Dutton, R., W., Alvarez, T., Arledge, L. 1984: 757-760
• Lump Partitioning of IC Bipolar Transistor Models for High Frequency Applications Chan, N., Dutton, R., W. 1984
• PISCES II: Poisson and Continuity Equation Solver Stanford Electronics Laboratories Pinto, M., R., Rafferty, C., S., Dutton, R., W. 1984
• Quantum Mechanical Considerations and Electrical Characterization of Metal (Silicide)-Silicon Interfaces Shenai, K., Sangiorgi, E., Saraswat, K., C., Swanson, R., M., Dutton, R., W. 1984
• Computer-Aided Process Modeling for Design and Process Control Silicon Processing, ASTM STP Dutton, R., W., Fahey, P., M., Doganis, K., Mei, L., Lee, H., G. edited by Gupta, D., C. American Society for Testing and Materials. 1984: 407-421
• Small Geometry MOS Intrinsic and Extrinsic Capacitance Measurement Test Structures for VLSI 1984 IEEE VLSI Workshop on Test Structures, San Diego, CA Oristian, J., E., Iwai, H., Walker, T., Dutton, R., W. 1984
• Computer-Aids for Analysis and Scaling of Extrinsic Devices IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Pinto, M., R., Dutton, R., W., Iwai, H., Rafferty, C., S. 1984: 288-291
• Small Geometry MOS Transistor Measurements and Observed Short and Narrow Channel Effects Iwai, H., Oristian, J., E., Walker, J., T., Dutton, R., W. 1984
• SOAP, Stanford Oxidation Analysis Program Stanford Electronics Laboratories, SEL 83-002 Chin, D., Dutton, R., W. 1983
• SUPREM III-Process Simulation Toward VLSI Ho, C., P., Plummer, J., D., Hansen, S., E., Dutton, R., W. 1983
• SUPREM III Stanford Electronics Laboratories, SEL 83-001 Hansen, S., E., Ho, C., P., Dutton, R., W. 1983
• Resistance Extraction from Mask Layout Data IEEE Transactions on Computer Aided Design Horowitz, M., A., Dutton, R., W. 1983; 3 (2): 145-150
• VLSI Process Modeling--SUPREM III IEEE Trans. Electron Devices Ho, C., P., Plummer, J., D., Hansen, S., E., Dutton, R., W. 1983; 11 (30): 1438-1453
• Computer-Aided Design of Integrated Circuit Fabrication Processes for VLSI Devices ICL 17-79, Stanford Electronics Laboratories, Technical Report No. TR DXG501-83 Plummer, J., D., Dutton, R., W., Gibbons, J., F., Helms, C., R., Meindl, J., D., Tiller, W., A. 1983
• Two-Dimensional Compaction Strategies Wolf, W., Mathews, R., Newkirk, J., Dutton, R., W. 1983
• The Role of Point Defects in VLSI Processing Lin, A., M., Dutton, R., W., Plummer, J., D. 1983
• An Overview of Process Models and Two-Dimensional Analysis Tools Stanford Electronics Laboratories, Technical Report No. G201-13 Dutton et al, R., W. 1982
• Stresses in Local Oxidation IEEE International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, CA Chin, D., Oh, S., Y., Hu, S., M., Dutton, R., W., Moll, J., L. 1982: 228-232
• SUXES, Stanford University Extractor of Model Parameters (Users Manual) Stanford Electronics Laboratories Doganis, K., Dutton, R., W. 1982
• Modeling Latch-Up in CMOS Integrated Circuits IEEE Trans. on CAD of IC and S. Estreich, D., B., Dutton, R., W. 1982; 4 (1): 157-162
• Modeling of Polycrystalline in Silicon Structures for Integrated Circuit Fabrication Process NATO Advanced Study Institute on Process and Device Simulation for MOS-VLSI Circuits, Urbino, Italy Mei, L., Dutton, R., W., Hansen, S., E. 1982
• Analysis of Nonplanar Devices NATO Advanced Study Institute on Process and Simulation for MOS-VLSI Circuits, Urbino Greenfield, J., A., Price, C., H., Dutton, R., W. 1982
• Path Delay Computation for Integrated Systems Al-Hussein, H., K., Dutton, R., W. 1982
• Two-Dimensional Process Simulation-SUPRA NATO Advanced Study Institute on Process and Device Simulation for MOS-VLSI Circuits, Urbino, Italy Kump, M., R., Dutton, R., W. 1982
• Supplementary Report on SEDAN II Stanford Electronics Laboratory, Stanford University, Technical Report No. G201-12 Yu, Z., Chang, G., Y., Dutton, R., W. 1982
• Two-Dimensional Simulation of Local Oxidation Chin, D., Oh, S., Y., Hu, S., M., Dutton, R., W. 1982
• Two-Dimensional Modeling of Local Oxidation DRC Chin, D., Dutton, R., W., Hu, S., M. 1982
• Computer-Aided Design of Integrated Circuit Fabrication Process for VLSI Devices ICL.17-79, Stanford Electronics Laboratories Plummer, J., D., Dutton, R., W., Gibbons, J., F., Helms, C., R., Meindl, J., D., Tiller, W., A. 1982
• Supplementary Report on SEDAN II Stanford Electronics Laboratory Yu, Z., Chang, G., Y., Dutton, R., W. 1982
• Process Simulation---Physical and Numerical Considerations NASECODE II, Dublin, Ireland Dutton, R., W., Hansen, S., E. 1981
• Modeling and Measurement of Impurity Diffusion in Polysilicon Grains Kump, M., R., Swaminathan, B., Dutton, R., W. 1981
• Two-Dimensional Process Modeling for High Density (LOCOS) Technology Dutton, R., W., Mei, L., Chin, D., Kump, M. 1981
• Simplified Two-Dimensional Analysis for Time-Dependent Carrier Transport and Impurity Redistribution Dutton, R., W., Lee, H., G., Oh, S., Y. 1981
• Computer Aided Design of Integrated Circuit Fabrication Processes for VLSI Devices ICL 17-79, Stanford Electronics Laboratory Plummer, J., D., Dutton, R., W., Gibbons, J., F., Helms, C., R., Meindl, J., D., Tiller, W., A. 1981
• Two-Dimensional Low Concentration Boron Profiles: Modeling and Measurement IEEE Trans. Electron Devices Lee, H, G., Dutton, R., W. 1981; 10 (28): 1136-1147
• The Growth of Oxidation Stacking Faults and the Point Defect Generation at Si-SiO Interface During Thermal Oxidation of Silicon J. Electrochem. Soc. Lin, A., M., Dutton, R., W., Antoniadis, D., A., Tiller, W., A. 1981; 5 (128): 1121-1130
• Stanford Overview in VLSI Research IEEE Circuits and Systems, Chicago Dutton, R., W., van Cleemput, W., M. 1981
• Computer Simulation in Silicon Epitaxy J. Electrochem. Soc. Reif, R., Dutton, R., W. 1981; 4 (128): 909-918
• Practical Considerations in Technology-Oriented Device Analysis Dutton, R., W., Price, C., H. 1981
• Position Statement--Tools for Design Automation from a University Point of View Dutton, R., W. 1981
• SUPRA - Stanford University Process Analysis Program Stanford Electronics Laboratory Chin, D., Kump, M., R., Dutton, R., W. 1981
• Modeling of High-Speed, Large-Signal Transistor Switching Transients from S-Parameter Measurements IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Ikawa, Y., Eisenstadt, W., R., Dutton, R., W. 1981: 608-611
• Optimization of IC Processes Using SUPREM Stanford Electronics Laboratory Doganis, K., Dutton, R., W., Gonzalez, A., G. 1981
• Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation IEEE Trans. Electron Devices Greenfield, J., A., Dutton, R., W. 1980; 8 (27): 1520-1532
• Two-Dimensional Analysis for Device Modeling Technical Report No. G201-7, Stanford Electronics Laboratory Greenfield, J., A., Hansen, S., E., Dutton, R., W. 1980
• Segregation of Arsenic to the Grain Boundaries in Polycrystalline Silicon J. Electrochem. Soc. Swaminathan, B., Demoulin, E., Sigmon, T., W., Dutton, R., W., Reif, R. 1980; 10 (127): 2227-2229
• A Surface Kinetics Model for Plasma Etching Mei, L., Chen, S., Dutton, R., W. 1980
• Transient Analysis of MOS Transistors IEEE Trans. Electron Devices Oh, S., Y., Ward, D., E., Dutton, R., W. 1980; 8 (27): 1571-1578
• Process Design Using Coupled 2D Process and Device Simulations IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Chin, D., J., Kump, M., R., Lee, H., G., Dutton, R., W. 1980: 223-226
• Enhanced Diffusion in the Single Crystal Silicon Substrate During Oxidation of a Deposited Polysilicon Doping Source Swaminathan, B., Mei, L., Lin, A., M., Dutton, R., W. 1980
• Computer Modeling for VLSI Dutton, R., W. 1980
• Computer Aided Engineering of Semiconductor Integrated Circuits ICL 17-78, Stanford Electronics Laboratory Meindl, J., D., Dutton, R., W., Gibbons, J., F., Helms, C., R., Plummer, J., D., Tiller, W., A. 1980
• Process Modeling of Multilayer Structures Involving Polycrystalline Silicon IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Mei, L., Swaminathan, B., Dutton, R., W. 1980: 219-222
• Process and Device Simulation for VLSI Modeling University of Maryland, UCLA Dutton, R., W. 1980
• Two-Dimensional Process Modeling for High-Density (LOCOS) Technology Dutton, R., W., Mei, L., Kump, M., R. 1980
• Computer Simulation in Silicon Epitaxy ECS Extended Abstracts, Boston, MA Reif, R., Dutton, R., W. 1979: 352-358
• A Desktop-Computer Based Process Control and Device Characterization System Khalily, E., Lin, A., M., Schuchard, R., A., Dutton, R., W., Daseking, H. 1979
• One-Dimensional Semiconductor Device Analysis (SEDAN) SEL 78-020, Stanford Electronics Laboratory D'Avanzo, D., C., Vanzi, M., Dutton, R., W. 1979
• Computer-Aided Engineering of Semiconductor Integrated Circuits ICL 7-77, Stanford Electronics Laboratory Meindl, J., D., Dutton, R., W., Gibbons, J., F., Plummer, J., D., Tiller, W., A., Saraswat, K., C. 1979
• The Lateral Effect of Oxidation-Enhanced Diffusion (LOED) in <100> Silicon Lin, A., M., Antoniadis, D., A., Dutton, R., W. 1979
• Measurement of Two-dimensional Profiles Near Locally Oxidized Regions Lee, H., G., Dutton, R., W. 1979
• Bulk Punchthrough Characterization of Submicron Transistor Using Poisson's Solution Demoulin, E., Barnes, J., J., Dutton, R., W. 1979
• The Rate-Control Model of Oxidation-Stacking Faults Growth in Silicon ECS Meeting, Los Angeles, CA Lin, A., M., Antoniadis, D., A., Dutton, R., W., Tiller, W., A. 1979
• The Lateral Effect of Oxidation on Boron Diffusion in <100> Silicon Appl. Phys. Lett. Lin, A., M., Dutton, R., W. 1979; 8 (27): 1520-1532
• Short-Channel MOSFET's in the Punchthrough Current Mode IEEE ED/JSSC Joint VLSI Special Issue Barnes, J., J., Shimohigashi, K., Dutton, R., W. 1979; 2 (14): 368-375
• Sensitivity of Electrical Parameters to Fabrication Variables for a Phosphorus Bipolar Process ECS Extended Abstracts, Boston, MA Khalily, E., Dutton, R., W. 1979: 369-372
• Process Statistics of Submicron MOSFET's IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington DC Demoulin, E., Greenfield, J., A., Dutton, R., W., Chatterjee, P., K., Tasch Jr., A., F. 1979: 34-37
• Process Simulation for Device Design and Control 1979 ISSCC Digest of Technical Papers Dutton, R., W., Antoniadis, D., A. 1979: 244-245
• On Redistribution of Boron During Thermal Oxidation of Silicon J. Electrochem. Soc. Lee, H, G., Dutton, R., W., Antoniadis, D., A. 1979; 11 (126): 2001-2007
• A Simplified Two-Dimensional Analysis of MOS Devices Oh, S., Y., Dutton, R., W. 1979
• Oxidation Rate Dependence of B and P Oxidation-Enhanced Diffusions in <100> Silicon ECS Extended Abstract, Boston, MA. Lin, A., M., Dutton, R., W., Antoniadis, D., A. 1979: 356-359
• Oxidation-Enhanced Diffusion of Arsenic and Phosphorus in Near-Intrinsic <100> Silicon Appl. Phys. Lett. Antoniadis, D., A., Lin, A., M., Dutton, R., W. 1978; 12 (33): 1030-1033
• Latch-Up in CMOS Integrated Circuits Estreich, D., B., Dutton, R., W. 1978
• Characteristics of Short Channel MOSFETs in the Punch-Through Current Mode Shimohigashi, K., Barnes, J., J., Dutton, R., W. 1978
• SUPREM II -- A Program for IC Process Modeling and Simulation SEL 78-020, Stanford Electronics Laboratory Antoniadis, D., A., Hansen, S., E., Dutton, R., W. 1978
• High Speed Implementation and Experimental Evaluation of Multilayer Spreading Resistance Analysis J. Electrochem. Soc. D'Avanzo, D., C., Rung, R., D., Gat, A., Dutton, R., W. 1978; 7 (125): 1170-1176
• Process Modeling for IC Device Technologies Dutton, R., W., Price, C., H., Husain, I., Antoniadis, D., A. 1978
• Modeling Latch-Up in CMOS Integrated Circuits Estreich, D., B., Dutton, R., W. 1978
• Characteristics of Short Channel MOSFETS in the Punch-through Current Mode Shimohigashi, K., Barnes, J., J., Dutton, R., W. 1978
• An Analysis of Latch-up Prevention in CMOS IC’s Using an Epitaxial-buried Layer Process Estreich, D., B., Ochoa Jr., A., Dutton, R., W. 1978
• Statistical Circuit Simulation on Computer Aided Design Divekar, D., A., McCalla, W., J., Dutton, R., W. 1978
• Computer Aided Engineering of Semiconductor Integrated Circuits SEL 78-011, Stanford Electronics Laboratory Meindl, J., D., Saraswat, K., C., Dutton, R., W., Gibbons, J., F., Tiller, W., Plummer, J., D. 1978
• Model Parameter Correlations in Statistical Circuit Simulation Divekar, D., A., Dutton, R., W. 1978
• Coupling of Process and Device Simulation for VLSI WESCON Dutton, R., W., Oh, S., Y. 1978
• A Charge-Oriented Model for MOS Transistor Capacitances IEEE J. Solid-State Circuits Ward, D., E., Dutton, R., W. 1978; 5 (13): 703-708
• Integrated Systems and Technologies in Stanford Curricula ISHM, Albuquerque, NM Dutton, R., W., Linvill, J., G. 1977
• Modeling of Moving Boundaries During Semiconductor Fabrication Processes Dutton, R., W., Antoniadis, D., A. 1977
• SUPREM I -- A Program for IC Process Modeling and Simulation Stanford Electronics Laboratory Technical Report, SEL 77-006 Antoniadis, D., A., Hansen, S., E., Dutton, R., W., Gonzalez, A., G. 1977
• Bipolar IC Device Statistics - An Experimental Study Divekar, D., A., Dutton, R., W., McCalla, W., J. 1977
• Oxidation and Epitaxy Stanford Electronics Laboratory Technical Report, Technical Report 5021-1 Dutton et. al, R., W. 1977
• Technology Modeling for IC Fabrication Modeling Semiconductor Devices (Journees D' Electronique 1977), Lausanne, Switzerland Dutton, R., W., Antoniadis, D., A. 1977
• Effects of the Diffused Impurity Profile on the DC Characteristics of VMOS and DMOS Devices IEEE J. Solid-State Circuits D'Avanzo, D., C., Combs, S., R., Dutton, R., W. 1977; 4 (12): 356-362
• Bipolar Models for Statistical IC Design Process and Device Modeling for Integrated Circuit Design Dutton, R., W., Divekar, D., A. 1977
• Stanford Electronics Laboratory Technical Report Technical Report 5021-2 Dutton, R., W., Divekar, D., A. 1977
• Modeling Integrated Injection Logic (I2L) Performance and Operational Limits IEEE J. Solid-State Circuits Estreich, D., B., Dutton, R., W. 1977; 5 (12): 450-462
• Invited Lectures on Process Models, Statistical Models and SUPREM Dutton et. al, R., W. 1977
• Local Truncation Error Control for Circuit Simulators Young, T., K., Dutton, R., W. 1977
• Modeling I2L Performance and Operational Limits IEEE ISSCC, Technical Digest Estreich, D., B., Dutton, R., W. 1977: 46-47
• An Integrated Injection Logic I2L Macromodel WESCON 77, Paper 11/2, WESCON Technical Program Estreich, D., B., Dutton, R., W. 1977: 1-9
• A Charge-Oriented Model for MOS Transistor Capacitances Ward, D., E., Dutton, R., W. 1977
• Spreading Resistance of Impurity Profile Stanford Electronics Laboratory Technical Report, SEL 76-004 D'Avanzo, D., C., Rung, R., D., Dutton, R., W. 1977
• A Computer Aided Design Model for High Voltage MOS (DMOS) Transistors IEEE J. Solid-State Circuits Pocha, M., D., Dutton, R., W. 1976; 5 (11): 718-726
• High Speed Multilayer Corrections for Spreading Resistance D'Avanzo, D., C., Dutton, R., W. 1976
• An Integrated Injection Logic (I2L) Macromodel Including Current Redistribution Effect IEEE J. Solid-State Circuits Estreich, D., B., Dutton, R., W., Wong, B., W. 1976; 5 (11): 648-657
• A Two-Lump Transistor Model for Computer Circuit Simulation IEEE J. Solid-State Circuits Divekar, D., A., Dutton, R., W. 1976; 5 (11): 726-730
• Mini-MSINC--A minicomputer Simulator for MOS Circuits with Modular Built-in Model IEEE J. Solid-State Circuits Young, T., K., Dutton, R., W. 1976; 5 (11): 730-732
• Characterization and Modeling of Simultaneously Fabricated DMOS and VMOS Transistors Combs, S., R., D'Avanzo, D., C., Dutton, R., W. 1976
• Boron Redistribution after Oxidation Rodoni, M., Buneman, O., Dutton, R., W. 1976
• Modeling Integrated Injection Logic Asilomar, Fall Estreich, D., B., Dutton, R., W. 1976
• Minicomputer Calculation of the DC Operating Point of Bipolar Circuits Stanford Electronics Laboratory Technical Report, SEL 76-012 Freret, J., P., Dutton, R., W. 1976
• Successful Circuit Simulation Using Minicomputers Freret, J., P., Dutton, R., W. 1976
• CAD Modeling of the Two-Terminal Uniform Distributed RC Line Gerzberg, L., Dutton, R., W., Meindl, J., D. 1975
• Lump Partitioning of Bipolar Junction Transistor Models for High Frequency Application Chan, N., Linvill, J., G., Dutton, R., W. 1975
• DMOS Experimental and Theoretical Study Rodgers, T., J., Asai, S., Pocha, M., D., Dutton, R., W., Meindl, J., D. 1975
• of Computer-Aided Design Techniques to Process, Device, and Circuit Designs Stanford Electronics Laboratory Technical Report, SEL-75-017 Dutton, R., W. 1975
• Bipolar Transistor Modeling of Avalanche Generation for Computer Circuit Simulation IEEE Trans. Electron Devices Dutton, R., W. 1975; 6 (22): 334-338
• A Monolithic Analog Signal Processor for Ultrasonic Imaging Systems Mussman, H., E., Dutton, R., W., Meindl, J., D. 1975
• Fabrication Process Modeling Applied to IC npn Transistors Using a Minicomputer Gonzalez, A., G., Combs, S., R., Gill, R., W., Dutton, R., W. 1975
• An Experimental and Theoretical Analysis of Double-Diffused MOS Transistors IEEE J. Solid-State Circuits Rodgers, T., J., Asai, S., Pocha, M., D., Dutton, R., W., Meindl, J., D. 1975; 5 (10): 322-331
• Threshold Voltage Controllability in Double Diffused-MOS Transistors IEEE Trans. Electron Devices Pocha, M., D., Gonzalez, A., G., Dutton, R., W. 1974; 12 (21): 778-784
• MSINC- A Modular Simulator for Integrated Nonlinear Circuits with MOS Model Example Young, T., K., Dutton, R., W. 1974
• Extraction and Sensitivity of Parameters for Higher-Order MOS Models Young, T., K., Dutton, R., W. 1974
• MSINC - A MOS Simulator for Integrated Nonlinear Circuits with Modular Built-in Model Stanford Electronics Laboratory Technical Report, SEL-74-038 Young, T., K., Dutton, R., W. 1974
• Techniques and Applications of Computer-Aided Circuit Simulation for Integrated Circuit and System Design. Part II: CAD Applications Stanford Electronics Laboratory Technical Report, SEL-74-017 Dutton, R., W. 1974
• Techniques and Applications of Computer-Aided Circuit Simulation for Integrated Circuits and System Design. Part I: CAD Techniques Stanford Electronics Laboratory Technical Report, SEL-74-005 Dutton, R., W. 1974
• Threshold Voltage Controllability in Double Diffused-MOS Transistors IEEE International Electron Devices Meeting (IEDM) Technical Digest, Washington, D.C. Pocha, M., D., Gonzalez, A., G., Dutton, R., W. 1973: 68-71
• Large Grain Tellurium Thin Films Thin Solid Films Dutton, R., W., Muller, R., S. 1972; 11: 229-236
• Electrical Properties of Tellurium Thin Films Dutton, R., W., Muller, R., S. 1971
• Forward Current-Voltage and Switching Characteristics of p+-n-n+ (Epitaxial) Diodes IEEE Trans. Electron Devices Dutton, R., W., Muller, R., S. 1969; 16: 458-467
• Thin Film CdS-CdTe Heterojunction Diodes Solid-State Electronics Dutton, R., W., Muller, R., S. 1968; 11: 749-756
• Computer-Aided Design of Integrated Circuits Fabrication Processes for VLSI Devices ICL 17-79, Stanford Electronics Laboratories, Technical Report No. TR DXG501-84 Plummer, J., D., Dutton, R., W., Gibbons, J., F., Helms, C., R., Meindl, J., D., Tiller, W., A. 1894