Goal
Hardware/software systems must become easier and more fun to develop. We aim to enable a more agile hardware development flow, to quickly and easily modify an existing design, letting us play with the resulting system.
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Co-ordinated by our partner Jeff Parkhurst, Intel provides direct support for faculty and staff including Professors Mark Horowitz, Pat Hanrahan and Clark Barrett along with Dr. Stephen Richardson. Students and post-docs involved with the project include those with direct support---James Hegarty, Jing Pu, Ross G. Daly, Jeff Ou Setter, Leonard Truong and Caleb Donovick---plus others. For more information see our...
Open Source Pledge
Center researchers pledge to use and develop open-source hardware and software, and it is the intention of all Agile Hardware Center researchers that any hardware and software will be released under an open source model, such as the BSD open source license. The center is open to all Stanford faculty who share this goal.
Stanford AHA! Agile Hardware Center
While advances in software tools and frameworks have enabled individuals to create interesting new products in reasonable time frames, hardware designs take large teams multiple years. This disparity in required effort decreases hardware innovation and interest. To address this issue, we must make hardware/software systems easier and more fun to develop, which means that we need to enable a more “agile” hardware development flow, making it possible to quickly and easily modify an existing design and play with the resulting system. To foster this goal of agile hardware design, we built the Stanford AHA! Agile Hardware Center, an Intel Science and Technology Center at Stanford and co-located with our partners at UC Berkeley.
As part of our initial efforts within the center, we propose to create an open source hardware/software tool chain to rapidly create and validate alternative hardware implementations, and a new open-source RISC-V/CGRA SoC system that will enable rapid execution/emulation of the resulting design.
Tool Chain
To support agile practices, our research will create a new tool chain for design and testing of unified hardware/software systems optimized for rapid design iteration. We aim to create the right interfaces in the generated hardware and the tool chain to allow both to be leveraged in future hardware projects. A common theme underlying this project is taking modern software engineering ideas and applying them to hardware design.
Coarse Grain Reconfigurable SoC
To further simplify the hardware design process, we will create an SoC combining open source Linux with RISC-V cores and a CGRA optimized for image processing. Our tool chain will let designers seamlessly move from writing application code to running the application on the SoC. Accomplishing smooth cooperation between CPU and specialized hardware requires software connectors that first hook the hardware to the OS, and then join application software to the resulting OS ports, services and/or drivers.
Improved SMT Solvers
From high-level validation to optimization to layout, agility requires replacing manual efforts with efficient automated tools wherever possible. Currently, SMT (satisfiability modulo theory) solvers are used in design automation for a wide range of tasks. But their performance is often a bottleneck, and the applications frequently require optimization in addition to feasibility checking. We aim to dramatically improve the performance of SMT solvers for hardware analysis and to add capabilities for optimization.
